Displaying 7 results from an estimated 7 matches for "geraint0923".
2012 Jul 20
2
[LLVMdev] Help with Instruction Expansion on Mips
...struction when compiling, however, it usually cause a 'can not
select ...' error when using 'short' data type in source code.
Then I tried to expand these instructions in EmitInstrWithCustomInserter in
file lib/Target/Mips/MipsISelLowering.cpp, just as commit in:
https://github.com/geraint0923/LLVM-ThuMips/commit/6a9ca907f3e945c2bb1f9627e0e5fdcbd7964da2
It works fine for lh and lhu, and fails for sh:
when expanding sh, there are four instruction, but in *.s generated by
modified llvm's llc, there are only two instructions which are both sb,
addiu and srl are gone.
Is there anything...
2012 Jul 23
0
[LLVMdev] How to disable register allocate optimization?
...nstrBuilder.h.
The register operand added to instruction sb should be a use, not a def
operand. So this function should be called,
BuildMI(BB, dl, TII->get(Mips::SB)).addReg(tmpReg1)
instead of
BuildMI(BB, dl, TII->get(Mips::SB), tmpReg1)
On Sat, Jul 21, 2012 at 11:41 AM, Yang Yang <geraint0923 at gmail.com> wrote:
> Hi everyone,
>
> I am trying to expand one instruction into multiple instructions on MIPS.
> For example, I try to expand:
> sh src, imm(dst)
> into:
> (1) sb src, imm(dst)
> (2) srl reg0, src, 8
> (3) sb r...
2012 Jul 21
2
[LLVMdev] How to disable register allocate optimization?
Hi everyone,
I am trying to expand one instruction into multiple instructions on MIPS.
For example, I try to expand:
sh src, imm(dst)
into:
(1) sb src, imm(dst)
(2) srl reg0, src, 8
(3) sb reg0, (imm+1)(dst)
Here, reg0 are created with createVirtualRegister.
However, instr(2) will not be emitted because reg0 is useless before reg0 is defined in instr(3), it is wrong!
So how to prevent the
2012 Jul 20
0
[LLVMdev] Help with Instruction Expansion on Mips
...r, it usually cause a
> 'can not select ...' error when using 'short' data type in source code.
> Then I tried to expand these instructions in
> EmitInstrWithCustomInserter in file
> lib/Target/Mips/MipsISelLowering.cpp, just as commit in:
>
> https://github.com/geraint0923/LLVM-ThuMips/commit/6a9ca907f3e945c2bb1f9627e0e5fdcbd7964da2
>
> It works fine for lh and lhu, and fails for sh:
> when expanding sh, there are four instruction, but in *.s generated by
> modified llvm's llc, there are only two instructions which are both
> sb, addiu and srl ar...
2012 Jul 20
2
[LLVMdev] Help with Instruction Expansion on Mips
...ever, it usually cause a 'can
> not select ...' error when using 'short' data type in source code.
> Then I tried to expand these instructions in EmitInstrWithCustomInserter
> in file lib/Target/Mips/MipsISelLowering.cpp, just as commit in:
>
>
> https://github.com/geraint0923/LLVM-ThuMips/commit/6a9ca907f3e945c2bb1f9627e0e5fdcbd7964da2
>
> It works fine for lh and lhu, and fails for sh:
> when expanding sh, there are four instruction, but in *.s generated by
> modified llvm's llc, there are only two instructions which are both sb,
> addiu and srl are...
2012 Jul 20
0
[LLVMdev] Help with Instruction Expansion on Mips
......' error when using 'short' data type
>> in source code.
>> Then I tried to expand these instructions in
>> EmitInstrWithCustomInserter in file
>> lib/Target/Mips/MipsISelLowering.cpp, just as commit in:
>>
>> https://github.com/geraint0923/LLVM-ThuMips/commit/6a9ca907f3e945c2bb1f9627e0e5fdcbd7964da2
>>
>> It works fine for lh and lhu, and fails for sh:
>> when expanding sh, there are four instruction, but in *.s
>> generated by modified llvm's llc, there are only two instructions
>> w...
2012 Jul 22
1
[LLVMdev] How to calculate the address in TableGen?
Hello everyone,
I would like to ask a question about the address calculation in TableGen.
I replace a definition in MipsInstrInfo.td:
def : Pat<(i32 (extloadi16_a addr:$src)), (LHu addr:$src)>;
to:
def : Pat<(i32 (extloadi16_a addr:$src)), (OR (LBu addr:$src), (SLL (LBu addr:($src+1)), 8))>;
However, it failed to compiled. It seems that ($src+1) is a wrong representation in TableGen.