search for: gddr5

...he object class definition 24a4ae8 drm/nouveau/instmem: tidy up the subdev class definition 64c672a drm/nouveau/pwr: implement a simple i2c stack 2e9dfe2 drm/nouveau/pwr: have rd/wr32 routines clobber data instead of addr 7321623 drm/nve0/fb: turn off some bits in 10f584 at init cb54dd2 drm/nve0/fb/gddr5: merge a fix from ddr3 for one of the timing settings b13d0e4 drm/nve0/fb/gddr5: yet another random 10f200 bit c814a60 drm/nvc0-/fb: hook up skeleton interrupt handler 7f39e59 drm/nve0/fb/gddr5: more 10f200 stuff 12642e3 drm/nve0/clk: report ddr memory frequency 1a894c0 drm/nouveau/fb/gddr5: make s...

...e-check Signed-off-by: Roy Spliet <nouveau at spliet.org> --- .../drm/nouveau/include/nvkm/subdev/bios/ramcfg.h | 12 +++--- drivers/gpu/drm/nouveau/nvkm/subdev/bios/rammap.c | 22 ++++++++-- drivers/gpu/drm/nouveau/nvkm/subdev/bios/timing.c | 2 + drivers/gpu/drm/nouveau/nvkm/subdev/fb/gddr5.c | 21 ++++++++-- drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf100.c | 49 ++++++++++++---------- 5 files changed, 71 insertions(+), 35 deletions(-) diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/ramcfg.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/ramcfg.h index 4560a52...

Hello, Attached a small patch that correctly identifies the DLLoff bit for >=GF100. Marked RFC because I haven't seen any GDDR5 samples that *enable* the DLL. I'd like to verify whether the DLL should be reset when enabled. Could increase likelihood of succesfull reclock. Ben: could you do some experiments with this bit to see if GDDR5 needs some DLL reset logic? Thanks, and happy reviewing! Roy

...; u32 reg[9]; - u32 mr[4]; + u32 mr[9]; u8 tCWL; diff --git a/drivers/gpu/drm/nouveau/nouveau_mem.c b/drivers/gpu/drm/nouveau/nouveau_mem.c index 1e1483e..1d290ab 100644 --- a/drivers/gpu/drm/nouveau/nouveau_mem.c +++ b/drivers/gpu/drm/nouveau/nouveau_mem.c @@ -626,6 +626,7 @@ nouveau_mem_gddr5_mr(struct nouveau_device *ndev, u32 freq, struct nouveau_pm_memtiming *boot, struct nouveau_pm_memtiming *t) { + u8 add_term; /* CMD/ADD termination */ if (len < 15) { t->drive_strength = boot->drive_strength; t->odt = boot->odt; @@ -644,18 +645,24 @@ nouveau...

this is my first patch on the list through git send-mail and I hope everything is set up right, sorry for the noise here, but I don't want to try with an empty mail :) as the subject already says, this patch fixes one of the more serious issues while reclocking gddr5 on kepler cards. It works for me and for a bunch of others I met on IRC. Karol Herbst (1): pll/gk104: fix PLL instability due to bad configuration with gddr5 drm/nouveau/nvkm/subdev/clk/Kbuild | 1 + drm/nouveau/nvkm/subdev/clk/pll.h | 5 +++ drm/nouveau/nvkm/subdev/clk/pllgk104.c |...

...s XP Home Edition HVM domU, you will see a yellow circle with exclamation mark and error code 10 in Device Manager for the 2nd Palit NVIDIA Geforce 8400 GS._ Then I noticed Jean David Techer uses a Geforce 560 Ti for his Xen VGA Passthrough. So 1-2 weeks ago I bought a EVGA Geforce GTX 560 1 GB GDDR5 for S$269. Same thing. Xen VGA Passthrough is only partially working or partial success. So I went back to the computer shop and exchanged my EVGA Geforce GTX 560 with a Gigabyte Geforce GTX 560 1 GB GDDR5, which costs S$289. Again, Xen VGA Passthrough is only partially working or partial succ...

...s XP Home Edition HVM domU, you will see a yellow circle with exclamation mark and error code 10 in Device Manager for the 2nd Palit NVIDIA Geforce 8400 GS._ Then I noticed Jean David Techer uses a Geforce 560 Ti for his Xen VGA Passthrough. So 1-2 weeks ago I bought a EVGA Geforce GTX 560 1 GB GDDR5 for S$269. Same thing. Xen VGA Passthrough is only partially working or partial success. So I went back to the computer shop and exchanged my EVGA Geforce GTX 560 with a Gigabyte Geforce GTX 560 1 GB GDDR5, which costs S$289. Again, Xen VGA Passthrough is only partially working or partial succ...

...]; } else - if (M0209E.v02_07 != 1) + if (M0209E.v02_07 > 2) return -EINVAL; train->mask |= 1 << M0205E.type; @@ -329,7 +330,47 @@ gt215_ram_train_type(struct nvkm_ram *ram, int i, u8 ramcfg, } static int -gt215_link_train_init(struct gt215_ram *ram) +gt215_ram_train_upload_gddr5(struct nvkm_ram *ram, + struct gt215_ram_train *train) +{ + struct nvkm_subdev *subdev = &ram->fb->subdev; + struct nvkm_device *device = subdev->device; + int i, j; + + static const u32 off[] = {0x00, 0x20, 0x04, 0x24}; + + if ((train->mask & 0x03c3) != 0x03c3) { + nvkm_info(...

...nitude away. - quite enough I/O bandwidth. Assuming off-chip TMDS/LVDS (sensible, given that neither the ARM core nor the FPGA have a high enough clock rate), the limiting I/O bandwidth is between the GPU and its video memory. That product claims it can do DDR3, which is not quite the same as GDDR5. You could try to trade-off between FPGA and the ARM core, but the ARM is only running at 800MHz. Maybe it's possible to get competitive performance, but it doesn't sound like a promising start. > i assumed that it would be possible to push other sections of the > gallium3d code...

Dear Gordan, I have a Gigabyte Geforce GTX 560. Is it possible to mod it into a Quadro? If it is possible, please give me the link with the list of steps to mod it into a Quadro. Is it a simple process? Thank you very much. -- Yours sincerely, Singapore Citizen Mr. Teo En Ming (Zhang Enming)

Dear Gordan, I have a Gigabyte Geforce GTX 560. Is it possible to mod it into a Quadro? If it is possible, please give me the link with the list of steps to mod it into a Quadro. Is it a simple process? Thank you very much. -- Yours sincerely, Singapore Citizen Mr. Teo En Ming (Zhang Enming)

...em but I noticed some error messages by Nouveau on dmesg. [ 1.963196] nouveau: detected PR support, will not use DSM [ 1.964517] nouveau 0000:01:00.0: NVIDIA GM107 (1171b0a2) [ 2.009352] nouveau 0000:01:00.0: bios: version 82.07.79.00.1e [ 2.115174] nouveau 0000:01:00.0: fb: 2048 MiB GDDR5 [ 2.115188] nouveau 0000:01:00.0: bus: MMIO read of 00000000 FAULT at 022554 [ IBUS ] [ 2.125653] nouveau 0000:01:00.0: bus: MMIO read of 00000000 FAULT at 10ac08 [ IBUS ] [ 2.786164] nouveau 0000:01:00.0: DRM: VRAM: 2048 MiB [ 2.786164] nouveau 0000:01:00.0: DRM: GART: 1048576 MiB [...

On Sun, Aug 21, 2011 at 12:48 AM, Nick Lewycky <nicholas at mxc.ca> wrote: > The way in which Gallium3D targets LLVM, is that it waits until it receives > the shader program from the application, then compiles that down to LLVM IR. > That's too late to start synthesizing hardware (unless you're planning to > ship an FPGA as the graphics card, in which case reprogramming

...are the code names? # dmesg | grep -i nouveau > [ 2.171473] fb: switching to nouveaufb from VESA VGA > [ 2.171595] nouveau 0000:01:00.0: NVIDIA GP107 (137000a1) > [ 2.286501] nouveau 0000:01:00.0: bios: version 86.07.39.80.5e > [ 2.287672] nouveau 0000:01:00.0: fb: 2048 MiB GDDR5 > [ 3.573113] nouveau 0000:01:00.0: DRM: VRAM: 2048 MiB > [ 3.573114] nouveau 0000:01:00.0: DRM: GART: 536870912 MiB > [ 3.573116] nouveau 0000:01:00.0: DRM: BIT table 'A' not found > [ 3.573117] nouveau 0000:01:00.0: DRM: BIT table 'L' not found > [ 3....

...) So can be used on this motherboard AMD Radeon graphics cards at all? If yes, does nouveau support these two Radeon cards with OpenGL of course: 1. VGA ASUS AMD Radeon R7 240, R7240-2GD3-L, 2GB DDR3, 128bit, 730/1800MHz, HDMI, DVI-D, D-sub 2. VGA ASUS R7260X-OC-2GD5, AMD ATI RADEON R7 260X, 2GB GDDR5, 128-bit, 1075/5000MHz, 2x DVI, 1x HDMI, 1 x Display Port, 1 x DVI to D-Sub adaptor, PCI Express 3.0 -- Best, Pali

...: [ 10.053162] fb: switching to nouveaufb from EFI VGA [ 10.053349] nouveau 0000:09:00.0: NVIDIA GM206 (126010a1) [ 10.174033] nouveau 0000:09:00.0: bios: version 84.06.0d.00.01 [ 10.174854] nouveau 0000:09:00.0: disp: dcb 15 type 8 unknown [ 10.178375] nouveau 0000:09:00.0: fb: 2048 MiB GDDR5 [ 10.202108] nouveau 0000:09:00.0: DRM: VRAM: 2048 MiB [ 10.202109] nouveau 0000:09:00.0: DRM: GART: 1048576 MiB [ 10.202113] nouveau 0000:09:00.0: DRM: TMDS table version 2.0 [ 10.202114] nouveau 0000:09:00.0: DRM: DCB version 4.1 [ 10.202116] nouveau 0000:09:00.0: DRM: DCB outp 00: 0100...

https://bugs.freedesktop.org/show_bug.cgi?id=33165 Summary: Nouveau + nvidia GT240 = unworkable Product: xorg Version: 7.5 Platform: x86 (IA32) OS/Version: Linux (All) Status: NEW Severity: normal Priority: medium Component: Driver/nouveau AssignedTo: nouveau at lists.freedesktop.org

...BIOS init table 4 at offset 0x874A [ 1.279905] [drm] nouveau 0000:01:00.0: Parsing VBIOS init table at offset 0x87AF [ 1.299888] [drm] nouveau 0000:01:00.0: 0x87AF: Condition still not met after 20ms, skipping following opcodes [ 1.305265] [drm] nouveau 0000:01:00.0: Detected 1536MiB VRAM (GDDR5) [ 1.305284] [drm] nouveau 0000:01:00.0: 512 MiB GART (aperture) [ 1.324224] [drm] nouveau 0000:01:00.0: 0 available performance level(s) [ 1.324226] [drm] nouveau 0000:01:00.0: c: core 50MHz shader 101MHz memory 135MHz voltage 963mV fanspeed 40% [ 1.616099] [drm] nouveau 0000:01:00.0:...

https://bugs.freedesktop.org/show_bug.cgi?id=100423 Bug ID: 100423 Summary: MMIO read of 00000000 FAULT at 022554 [ IBUS ] Product: xorg Version: unspecified Hardware: Other OS: All Status: NEW Severity: normal Priority: medium Component: Driver/nouveau Assignee: nouveau at

...000:05:00.0: NVIDIA GP107 (137000a1) [ 1.107079] nouveau 0000:05:00.0: bios: version 86.07.42.00.4a [ 1.107391] nouveau 0000:05:00.0: gr: failed to load firmware "gr/sw_nonctx" [ 1.107494] nouveau 0000:05:00.0: gr: failed to load gr/sw_nonctx [ 1.107857] nouveau 0000:05:00.0: fb: 4096 MiB GDDR5 [ 1.124158] nouveau 0000:05:00.0: DRM: VRAM: 4096 MiB [ 1.124268] nouveau 0000:05:00.0: DRM: GART: 536870912 MiB [ 1.124381] nouveau 0000:05:00.0: DRM: BIT table 'A' not found [ 1.124493] nouveau 0000:05:00.0: DRM: BIT table 'L' not found [ 1.124604] nouveau 0000:05:00.0: DRM: TMDS...