Displaying 2 results from an estimated 2 matches for "fspsrr".
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fpsr
2009 Mar 24
2
[LLVMdev] Reducing .td redundancy
...that will let me do this (replace SOME_CONCAT with
an appropriate operator):
(WARNING! Hacked-up tablegen ahead!)
multiclass sse_fp_binop_bitwise_rm<bits<8> opc, string OpcodeStr,
SDNode OpNode> {
// Vector operation emulating scalar (fp)
def FsPSrr : PSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:
$src2),
!strconcat(OpcodeStr, "ps"\t{$src2, $dst|$dst, $src2}"),
[(set FR32:$dst, (!SOME_CONCAT("x86f", OpNode) FR32:
$src1, FR32:$src2))]>;
// Vector operati...
2009 Mar 24
0
[LLVMdev] Reducing .td redundancy
...ou try a simpler example on me? :)
-Chris
>
>
> (WARNING! Hacked-up tablegen ahead!)
>
> multiclass sse_fp_binop_bitwise_rm<bits<8> opc, string OpcodeStr,
> SDNode OpNode> {
> // Vector operation emulating scalar (fp)
> def FsPSrr : PSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1,
> FR32:
> $src2),
> !strconcat(OpcodeStr, "ps"\t{$src2, $dst|$dst,
> $src2}"),
> [(set FR32:$dst, (!SOME_CONCAT("x86f", OpNode)
> FR32:
> $src1,...