Displaying 4 results from an estimated 4 matches for "fpuaoffsetclass".
2018 Sep 10
3
How to avoid multiple registers definitions in customInserter.
...OUTADDRegisterClass:$FA_ROUTADD,(or FPUaOffsetOperand:$OffsetA,FPUaOffsetOperand:$OffsetB))],NoItinerary>
{let usesCustomInserter = 1;}
The instructions selection and registers allocation are performed with the pseudo.
%4:fpuaoffsetclass = LOAD_A_r @a; FPUaOffsetClass:%4
%5:fpuaoffsetclass = LOAD_A_r @b; FPUaOffsetClass:%5
%6:fpuaroutaddregisterclass = OR_A_oo killed %5, killed %4, implicit-def dead %rflaga; FPUaROUTADDRegisterClass:%6 FPUaOffsetClass:%5,%4
%7:fpuaoffsetclass = COPY %6; FPUaOffsetClass:%7 FP...
2018 Apr 23
2
pre-RA scheduling/live register analysis optimization (handle move) forcing spill of registers
...in order to avoid frequent spill out of FA_ROUTMUL, I systematically copy the result of FMUL_A_oo to a virtual register through a COPY_TO_REGCLASS.
def : Pat<(fdiv f32:$OffsetA, f32:$OffsetB), (COPY_TO_REGCLASS (FDIV_A_oo FPUaOffsetOperand:$OffsetA,FPUaOffsetOperand:$OffsetB),FPUaOffsetClass)>;
The instruction lowering goes as expected all instances of FMUL_A_oo are followed by a COPY, freeing the usage of FPUaROUTMULRegisterClass.
These COPY are at positions 64B and 112B in the example below. So far, so good.
My problem arise in some pre-RA instruction scheduling optimization mov...
2018 Sep 20
2
Errononous scheduling of COPY instruction.
Hi,
I've instruction scheduling problem that I cannot further investigate by myself... Could someone give me some clues?
After Instruction selection, here is part of the generated instruction.
NOP
MOV_AB_ro @s1, %fab_roff0
%6:fpuaoffsetclass = COPY %fab_roff0; FPUaOffsetClass:%6
MOV_A_oo %6, def %5; FPUaOffsetClass:%6,%5
MOVSUTO_A_iSLo 24575, def %7; FPUaOffsetClass:%7
The order of instruction is very important: the COPY shall take place after the MOV_AB_ro!
But during Instruction scheduling, these two instructions ha...
2018 Apr 12
2
How to specify the RegisterClass of an IMPLICIT_DEF?
...CIT_DEF followed by INSERT_SUBREGs. This approach is the one of the SPARC architecture.
def : Pat<(build_vector (f32 fpimm:$a1), (f32 fpimm:$a2)),
(INSERT_SUBREG(INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
(i32 (COPY_TO_REGCLASS (MOVSUTO_A_iSLo (bitcast_fpimm_to_i32 f32:$a1)), FPUaOffsetClass)), A_UNIT_PART),
(i32 (COPY_TO_REGCLASS (MOVSUTO_A_iSLo (bitcast_fpimm_to_i32 f32:$a2)), FPUaOffsetClass)), B_UNIT_PART)>;
This work quite well: an IMPLICIT_DEF:v2f32 is generated.
Selected selection DAG: BB#0 'vector2floatMulSum:entry'
SelectionDAG has 19 nodes:...