Displaying 2 results from an estimated 2 matches for "fpscr_nzcv".
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apsr_nzcv
2015 Sep 17
2
Register Number
...epresent a particular register. The 0x01 would be the
encoding used in generating the binary.
The D0 has id 14 on ARM because there are 13 other registers preceding it:
namespace ARM {
enum {
NoRegister,
APSR = 1,
APSR_NZCV = 2,
CPSR = 3,
FPEXC = 4,
FPINST = 5,
FPSCR = 6,
FPSCR_NZCV = 7,
FPSID = 8,
ITSTATE = 9,
LR = 10,
PC = 11,
SP = 12,
SPSR = 13,
D0 = 14,
...
-Krzysztof
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2015 Sep 17
2
Register Number
Dear all,
in my TestRegisterInfo.td file, I defined a register like this:
class TestReg<bits<6> enc, string name> : Register<name> {
let HWEncoding{5-0} = enc;
let Namespace = "TEST";
}
def D0 : TestReg<0x01, "d0">, DwarfRegNum<[1]>;
but when I compile, the result I have in TestGenAsmMatcher.inc is this:
case 'd': // 7