Displaying 9 results from an estimated 9 matches for "apsr_nzcv".
2010 Jul 12
0
[LLVMdev] build errors while cross compiling llvm-gcc for ARM
> ~/Desktop/Sanjeev/LLVM/llvm-2.7/Release/lib/libLLVMgold.so --eh-frame-hdr
> -melf_i386 -dynamic-linker /lib/ld-linux.so.2 /usr/lib/crt1.o
Ok, this way you're generating code for x86
> /usr/lib/crti.o
> /usr/local/lib/gcc/i686-pc-linux-gnu/4.2.0/crtbegin.o
> -L/usr/local/lib/gcc/i686-pc-linux-gnu/4.2.0 -L/usr/local/lib -lgcc
> --as-needed -lgcc_s --no-as-needed -lc -lgcc
2010 Jul 28
2
[LLVMdev] build errors while cross compiling llvm-gcc for ARM
.../../include -I../.././gcc/../libcpp/include
-I../.././gcc/../libdecnumber -I../libdecnumber -I/home/jal/llvm-2.7/include
-DL_mulsc3 -fvisibility=hidden -DHIDE_EXPORTS -c ../.././gcc/libgcc2.c -o
libgcc/./_mulsc3.o
/tmp/ccmyj0Hi.s: Assembler messages:
/tmp/ccmyj0Hi.s:60: Error: bad instruction `vmrs apsr_nzcv,fpscr'
/tmp/ccmyj0Hi.s:62: Error: bad instruction `vmrsvs apsr_nzcv,fpscr'
/tmp/ccmyj0Hi.s:71: Error: bad instruction `vmrs apsr_nzcv,fpscr'
/tmp/ccmyj0Hi.s:76: Error: bad instruction `vmrs apsr_nzcv,fpscr'
/tmp/ccmyj0Hi.s:83: Error: bad instruction `vmrs apsr_nzcv,fpscr'
/tmp/c...
2010 Jul 12
2
[LLVMdev] build errors while cross compiling llvm-gcc for ARM
Sorry for not explaining well.
After compiling with g++-cross
g++-cross -c a.c
I do link using this command
/gold_binutils/build/gold/ld-new -plugin
~/Desktop/Sanjeev/LLVM/llvm-2.7/Release/lib/libLLVMgold.so --eh-frame-hdr
-melf_i386 -dynamic-linker /lib/ld-linux.so.2 /usr/lib/crt1.o
/usr/lib/crti.o
/usr/local/lib/gcc/i686-pc-linux-gnu/4.2.0/crtbegin.o
2015 Sep 17
2
Register Number
...gisterInfo.inc. These numbers don't have any meaning
other than to represent a particular register. The 0x01 would be the
encoding used in generating the binary.
The D0 has id 14 on ARM because there are 13 other registers preceding it:
namespace ARM {
enum {
NoRegister,
APSR = 1,
APSR_NZCV = 2,
CPSR = 3,
FPEXC = 4,
FPINST = 5,
FPSCR = 6,
FPSCR_NZCV = 7,
FPSID = 8,
ITSTATE = 9,
LR = 10,
PC = 11,
SP = 12,
SPSR = 13,
D0 = 14,
...
-Krzysztof
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
hosted by The Linux Foundation
2015 Sep 17
2
Register Number
Dear all,
in my TestRegisterInfo.td file, I defined a register like this:
class TestReg<bits<6> enc, string name> : Register<name> {
let HWEncoding{5-0} = enc;
let Namespace = "TEST";
}
def D0 : TestReg<0x01, "d0">, DwarfRegNum<[1]>;
but when I compile, the result I have in TestGenAsmMatcher.inc is this:
case 'd': // 7
2019 Oct 08
2
PR43374 - when should comparing NaN values raise a floating point exception?
...send the optimized IR to codegen:
> define i32 @is_nan(float %x) {
> %cmp = fcmp uno float %x, 0.000000e+00
> %r = zext i1 %cmp to i32
> ret i32 %r
> }
>
> $ llc -o - fpexception.ll -mtriple=armv7a
> vmov s0, r0
> mov r0, #0
> vcmpe.f32 s0, s0
> vmrs APSR_nzcv, fpscr
> movwvs r0, #1
> bx lr
>
> We produced "vcmpe" for code that should never cause an FP exception. ARM
> codegen bug?
sorry, the arm code gen is right here, the bug is in clang.
>
> On Tue, Oct 1, 2019 at 5:45 AM Kristof Beyls <Kristof.Beyls at arm.co...
2011 May 26
2
[LLVMdev] LLVM CodeGen Engineer job opening with Apple's compiler team
Hi all,
LLVM CodeGen and Tools team at Apple is looking for exceptional compiler engineers. This is a great opportunity to work with many of the leaders in the LLVM community.
If you are interested in this position, please send your resume / CV and relevant information to evan.cheng at apple.com
Thanks,
Evan
Job description
The Apple compiler team is seeking an engineer who is strongly
2011 May 27
1
[LLVMdev] Question about ARM/vfp/NEON code generation
...r1, [r7, #-8]
vmov s1, r1
str r2, [r7, #-12]
vmov s2, r2
vldr.32 s3, [r7, #-4]
vldr.32 s4, [r7, #-8]
vmul.f32 s3, s3, s4
vstr.32 s3, [r7, #-16]
vldr.32 s4, [r7, #-12]
vcmpe.f32 s3, s4
vmrs apsr_nzcv, fpscr
vstr.32 s0, [sp, #16]
vstr.32 s2, [sp, #12]
vstr.32 s1, [sp, #8]
ble LBB20_2
@ BB#1: @ %bb
vldr.32 s0, [r7, #-16]
ldr r0, LCPI20_0
LPC20_0:
add r0, pc, r0
vcvt.f64.f32 d1, s0...
2019 Oct 01
5
PR43374 - when should comparing NaN values raise a floating point exception?
Hi,
I’ve been investigating https://bugs.llvm.org/show_bug.cgi?id=43374, which is about clang/llvm producing code that triggers a floating point exception when x is NaN, when targeting ARM, in the below code example.
int bar(float x) {
return x!=x ? 0 : 1;
}
The C99 standard states in section 7.12.14:
"""
The relational and equality operators support the usual mathematical