search for: fpgas

Not only do FPGAs not support recursion, we don’t even support calls! All user code must be inlined into one kernel/component, which is then used to create HDL for the FPGA. Mark From: Bruce Hoult <brucehoult at sifive.com> Sent: December 17, 2018 9:28 AM To: Mendell, Mark P <mark.p.mendell at intel.com&...

Hi, Would anyone be interested in developing a LatticeMico32 backend in LLVM? LatticeMico32 [1] is an open source microprocessor core designed by Lattice Semiconductor and typically used in FPGAs. It is comparable to the Microblaze processor that you already support. It is already supported by GNU Binutils and GCC (4.5+). It is used by the Milkymist [2] and RTEMS [3] projects. The Milkymist project would like to use the LLVM compiler toolchain as an alternative to GCC, which requires de...

...of help and information on writing an LLVM backend. And, my platform has no stack. Can you point me to any information that would specifically address creating a backend for this kind of platform? In previous wanderings, I thought I ran across a phrase "platforms with no stack such as FPGAs", but I can't find that mention, now. More thanks than I can type, JD Jones Software Engineer -- This message is intended for the addressee only and may contain Paragon Research Corporation (PRC) confidential or privileged information. Use or distribution of such confidential i...

...ks, Sébastien On Tuesday 18 May 2010 18:38:41 Sébastien Bourdeauducq wrote: > Hi, > > Would anyone be interested in developing a LatticeMico32 backend in LLVM? > > LatticeMico32 [1] is an open source microprocessor core designed by Lattice > Semiconductor and typically used in FPGAs. It is comparable to the > Microblaze processor that you already support. > > It is already supported by GNU Binutils and GCC (4.5+). It is used by the > Milkymist [2] and RTEMS [3] projects. The Milkymist project would like to > use the LLVM compiler toolchain as an alternative t...

....." > > > Today's Topics: > > 1. Implementing a flac-decoder in VHDL (Axel Reimer) > > > ---------------------------------------------------------------------- > > Message: 1 > Date: Tue, 22 Jan 2008 13:26:16 +0100 > From: Axel Reimer <mailinglists@fpgas.de> > Subject: [Flac-dev] Implementing a flac-decoder in VHDL > To: flac-dev@xiph.org > Message-ID: <4795E0E8.2060603@fpgas.de> > Content-Type: text/plain; charset=ISO-8859-15 > > Hello, > > my name is Axel Reimer and I am new to this mailing list. I subscribed >...

...one by the same ALU circuitry which delays the pipeline by its worstcase path timing. So, for modern processor hardware purposes, OR is exactly equal ADD. Transforming ADD to OR isn't strenght reduction at all. Maybe this is benefical only if you have a backend generating circuitry (programming FPGAs). I believe that in cases where ADD and OR are equivalent, LLVM prefers the latter because it's easier to reason about the bits in the result of an OR in complex cases. The x86 backend, for instance, transforms ORs in such cases back into adds, presumably in case it may be matched to an lea wh...

...can be analyzed by Ultimate Buchi Automizer (https://ultimate.informatik.uni-freiburg.de/downloads/BuchiAutomizer/). This is a tool that tries to prove termination or infinite execution for some programs. * We can check how many programs can be compiled by different high-level synthesis tools into FPGAs. We have tried LegUp and Vivado, for instance. * Our webpage contains a search box, so that you can get the closest programs to a given input program. Currently, we measure program distance as the Euclidian distance on Namolaru feature vectors. We do not currently provide inputs for those program...

...one by the same ALU circuitry which delays the pipeline by its worstcase path timing. So, for modern processor hardware purposes, OR is exactly equal ADD. Transforming ADD to OR isn't strenght reduction at all. Maybe this is benefical only if you have a backend generating circuitry (programming FPGAs). > > > - Is there a straight forward way to know if an instruction belongs to > a > > loop? (just curiosity) > > I'll defer to others on this one. > > > > > Thanks very much > > > > Daniel Nicacio > Best, > Matt > > > _______...

.... Before I start in on the actual implementation, I'd like to make sure that I'm on the right track. Any comments, suggestions, warnings, tips, etc would be greatly appreciated. Background ---------- There are a number of small as other embedded microprocessors that are often used in FPGAs such as Xilinx's Picoblaze, Lattice's Mico8, or Bernd Paysan's b16-small. I am developping a very small stack machine primarily for use inside FPGAs and ASICs. This serves roughly the same niche as the above processors, however from my perpsective, my design has a number of advantag...

...ealth of help and information on writing an LLVM backend. And, my platform has no stack. Can you point me to any information that would specifically address creating a backend for this kind of platform? In previous wanderings, I thought I ran across a phrase “platforms with no stack such as FPGAs”, but I can’t find that mention, now. More thanks than I can type, JD Jones Software Engineer This message is intended for the addressee only and may contain Paragon Research Corporation (PRC) confidential or privileged information. Use or distribution of such confidential information is s...

Hi Chris, The main benefit for LLVM to include SPIRV support directly is to increase the number of users and developers in the area of heterogeneous computing, e.g. GPUs, FPGAs, DSPs. We want to increase the number of such devices that LLVM natively supports by adding compilation to SPIRV due to the shortage of proprietary backends in upstream LLVM. Just to clarify we are currently suggesting to integrate the converter as a subproject of LLVM, similar to Clang or libcl...

...so I’ll assume your using some version of SHA-2 and are aware of the collision vulnerabilities in MD5 and (the more difficult to generate) collision vulnerabilities in SHA-1. Even so, “can’t be forged” sounds like snake oil, and is incontrovertibly incorrect (given enough time and enough parallel FPGAs). -- Posted via http://www.ruby-forum.com/. --~--~---------~--~----~------------~-------~--~----~ You received this message because you are subscribed to the Google Groups "Ruby on Rails: Talk" group. To post to this group, send email to rubyonrails-talk-/JYPxA39Uh5TLH3MbocFFw@public.gm...

...re is a free C compiler (very good, I must add). See: http://winavr.sf.net OR http://www.nongnu.org/avr-libc/ Also see: http://www.atmel.com and go the the products -> Microcontrollers -> AVR 8-bit RISC and take a look around. Or: http://www.avrfreaks.net/ (a users web site) If you like FPGAs and/or ASICs, you could go to: http://www.opencores.org Hope this may help you, I would take the project, but I have no time righ now. Maybe in about 1.5 months, when my degree work is done. c-ya! Ildefonso Camargo icamargo@unet.edu.ve ildefonso_camargo@yahoo.com >Message: 3 >Date: Tue,...

.... Before I start in on the actual implementation, I'd like to make sure that I'm on the right track. Any comments, suggestions, warnings, tips, etc would be greatly appreciated. Background ---------- There are a number of small as other embedded microprocessors that are often used in FPGAs such as Xilinx's Picoblaze, Lattice's Mico8, or Bernd Paysan's b16-small. I am developping a very small stack machine primarily for use inside FPGAs and ASICs. This serves roughly the same niche as the above processors, however from my perpsective, my design has a number of advantag...

On Feb 27, 2018, at 10:25 AM, Tom Stellard via llvm-dev <llvm-dev at lists.llvm.org> wrote: > On 02/27/2018 05:07 AM, Anastasia Stulova wrote: >>> SPIR-V does not have to be a part of LLVM for you to do this. You can add >>> the SPIR-V target to clang and then define a SPIR-V toolchain (i.e. clang/Driver/Toolchains) >>> that uses the external tool to translate

...ith decent 3D Graphics Engine would be as equally simple (the only FSF Hardware-Endorsed laptop product is that Loongson Leemote, by virtue of it having a 2D PCI Graphics IC and a 900mhz MIPS). the logic goes as follows: * one of the Gallium3D targets is LLVM. * one of LLVM's targets is Xilinx FPGAs (MicroBlaze). * the zynq-7000 7030 has 125k FPGA Logic Gates (and more) * with a TFP410 as the DVI driver, the OGP is done! now, given that this appears to be "too easy", i'd really _really_ appreciate some help checking the facts. and, also, if it turns out to be feasible, assessin...

...s://ultimate.informatik.uni-freiburg.de/downloads/BuchiAutomizer/). > > This is a tool that tries to prove termination or infinite execution > > for some programs. > > > > * We can check how many programs can be compiled by different > > high-level synthesis tools into FPGAs. We have tried LegUp and Vivado, > > for instance. > > > > * Our webpage contains a search box, so that you can get the closest > > programs to a given input program. Currently, we measure program > > distance as the Euclidian distance on Namolaru feature vectors. >...

Hi Daniel, > Hi folks, > > I couldn't find a specific XOR (OR and AND) optimization on llvm, and > therefore I am about to implement it. > But first I would like to check with you guys that it really does not exist. > > For a simple loop like this: > > nbits = 128; > bit_addr = 0; > while(nbits--) > { > bindex=bit_addr>>5; /* Index is

I am going to improve theora codec with dynamically changing way. In this case we want to change compression parameters like video_q, sharpness when a keyframe is generated. When i set video quality parameter using cpi-> pb.info.quality in CommpressKeyFrame in encoder_toplevel it will not change dynamically. Can you please help me to do this. Wich function should i cange to achieve my

...topic encompassing design/architecture, management, performance management, modeling and configuration/tooling: Design / Architecture: - Containers and OS-level virtualization (LXC, Docker, rkt, Singularity, Shifter, i.a.) - Hypervisor support for heterogeneous resources (GPUs, co-processors, FPGAs, etc.) - Hypervisor extensions to mitigate side-channel attacks ([micro-]architectural timing attacks, privilege escalation) - VM & Container trust and security models - Multi-environment coupling, system software supporting in-situ analysis with HPC simulation - Cloud reliability, fault-to...