Displaying 3 results from an estimated 3 matches for "flagreg".
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flagregs
2012 Dec 06
0
[LLVMdev] Register classes, reg unit weights calculation in tablegen
...terInfoEmitter::EmitRegUnitPressure(llvm::raw_ostream &, const llvm::CodeGenRegBank &, const std::string &): Assertion `RU.Weight < 256 && "RegUnit too heavy"' failed.
The reason for this is that I have constructed pred-operands to be of the register class type FlagRegs, which holds a big union of classes, so that I can generate code like
Cmp %1:RC1, 0
Brr #bb, if EQ:%1
Cmp %2:RC2, 0
Brr #bb, if EQ:%2
, where RC1 and RC2 (and others as well not shown here) both share common sub-registers, but are of different widths. This construct makes it easy to predi...
2012 Dec 11
0
[LLVMdev] FW: Register classes, reg unit weights calculation in tablegen
...terInfoEmitter::EmitRegUnitPressure(llvm::raw_ostream &, const llvm::CodeGenRegBank &, const std::string &): Assertion `RU.Weight < 256 && "RegUnit too heavy"' failed.
The reason for this is that I have constructed pred-operands to be of the register class type FlagRegs, which holds a big union of classes, so that I can generate code like
Cmp %1:RC1, 0
Brr #bb, if EQ:%1
Cmp %2:RC2, 0
Brr #bb, if EQ:%2
, where RC1 and RC2 (and others as well not shown here) both share common sub-registers, but are of different widths. This construct makes it easy to predi...
2011 Jan 31
0
[LLVMdev] Target code size
...odify the flag
register (overflow flag, zero flag, ...) are smaller that the ones that do
not modify the flag register.
So, I have basically 2 choices (you might have other ideas...):
1) In the InstrInfo.td, I indicate that all the arithmetic and bitwise
instructions modify the flags (using Defs = [FlagReg]).
The pros: it selects instructions that are smaller.
The cons: if I have a comparison whose result is used twice (or more),
and some arithmetic instructions are used in between, the comparison has to
be done again (the flags have been overwritten).
2) In the InstrInfo.td, the selection gene...