search for: flagregs

...terInfoEmitter::EmitRegUnitPressure(llvm::raw_ostream &, const llvm::CodeGenRegBank &, const std::string &): Assertion `RU.Weight < 256 && "RegUnit too heavy"' failed. The reason for this is that I have constructed pred-operands to be of the register class type FlagRegs, which holds a big union of classes, so that I can generate code like Cmp %1:RC1, 0 Brr #bb, if EQ:%1 Cmp %2:RC2, 0 Brr #bb, if EQ:%2 , where RC1 and RC2 (and others as well not shown here) both share common sub-registers, but are of different widths. This construct makes it easy to predic...

...terInfoEmitter::EmitRegUnitPressure(llvm::raw_ostream &, const llvm::CodeGenRegBank &, const std::string &): Assertion `RU.Weight < 256 && "RegUnit too heavy"' failed. The reason for this is that I have constructed pred-operands to be of the register class type FlagRegs, which holds a big union of classes, so that I can generate code like Cmp %1:RC1, 0 Brr #bb, if EQ:%1 Cmp %2:RC2, 0 Brr #bb, if EQ:%2 , where RC1 and RC2 (and others as well not shown here) both share common sub-registers, but are of different widths. This construct makes it easy to predic...

I am adding a new target to LLVM (a DSP processor). Resulting code size on an embedded system is as important as code efficiency. So my first question is: How to introduce code size criteria in the instruction selection ? Is there any scheme already in place for that purpose ? My second question is related to my target. On this target, arithmetic and bitwise instructions that modify the flag