Displaying 3 results from an estimated 3 matches for "fhonor".
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honor
2008 May 12
3
[LLVMdev] LLVM Exception Handling Changes
...exceptions
> cannot happen, then clear the bit. As the bits are cleared,
exception handlers
> can be deleted and dead loads (for example) can also be removed.
>
> This bit also exposes a lot of flexibility and control to the front-
end. In
> particular, gcc supports the -fhonor-snans flag, which would enable
the trap
> bit on (basically) all floating point operations. The presense of
this flag
> would trigger generation of the fcomi instruction instead of fucomi
(on X86)
> for example, and would inhibit optimizations that would break the
semantics of...
2010 Nov 21
0
[LLVMdev] Poor floating point optimizations?
I'm aware that there are IEEE requirements for floating point. But all C/C++
compilers like GCC or MSVC have unsafe/fast math switches that disable all
problems related to NaN/Inf/+-0/precision etc because in some applications those
are not as important as performance (for example graphics calculation).
But as I understand, LLVM currently does not have such unsafe/fast math
optimizations
2010 Nov 21
2
[LLVMdev] Poor floating point optimizations?
Hi Bob,
> For example expressions like "1+x+1+x+1+x+1+x" (basically adding a lot of
> constants and variables) are complied to a long series off<add>s both in IR
> and
> assembly code.
> Both GCC and MSVC generates C1*x +C2 (mov + mul + add).
>
> I am new to using LLVM. I am using Visual Studio 2008 on Windows, targeting
> 32-bit X86 code. I'm using