search for: ffr

Displaying 20 results from an estimated 22 matches for "ffr".

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2011 Oct 17
1
simultaneously maximizing two independent log likelihood functions using mle2
...Holling Type II Equation holling2.pred = function(N0, a, h, P, T) { a * N0 * P * T/(1 + a * h * N0) } # Negative log likelihood function NLL.holling2 = function(a, h, P = 1, T = 1) { -sum(dbinom(Killed, prob = a * T * P/(1 + a * h * Initial), size = Initial, log = TRUE)) } # MLE statement FFR.holling2 = mle2(NLL.holling2, start = list(a = 0.012, h = 0.84), data = list(T = 14, P = 3)) I have my negative log likelihood function setup similarly to the above example. Again, my goal is to simultaneously estimate parameters from the same function for two years, such that I can test if...
2016 Nov 25
2
[RFC] Supporting ARM's SVE in LLVM
...d to increment to the induction variable is not even known at run time! Meaning, that's not a constant at all! Example: a[i] = b[ c[i] ]; ld1w z0.s, p0/z, [ c, i, lsl 2 ] ld1w z1.s, p0/z, [ b, z0.s, stxw 2 ] Now, z0.s load may have failed with seg fault somewhere, and it's up to the FFR to tell brka/brkb how to deal with this. Each iteration will have: * The same vector length *per process* for accessing c[] * A potentially *different* vector length, *per iteration*, for accessing b[] So, while <n x m x i32> could be constant on some vectors, even at compile time (if w...
2013 Apr 01
2
[LLVMdev] Instruction Implementation
hi all I have a question about implementing a new instruction which does this function f(x) = x + ceilf (x) .x is a single float i have already added the instruction in my backend in the .td file def SUBCEIL_S : FFR<0x11, 0x3, 16, (outs FGR32:$fd), (ins FGR32:$fs), "frac.s\t$fd, $fs", [(set (f32 FGR32:$fd), (fadd (f32 FGR32:$fs ),(f32 (ceilf FGR32:$fs))))] >; it makes and install correctly but when i ll try to write code to use this instruction there is no luck. Should i do something in I...
2003 May 22
2
libpri and zap lib
Hello all, I have some questions about the libpri and zap lib. I've sent mail to Mark for help. Also I wonder whether anyone else would be interested and helpful in them. I'm going to migrate a program to Wildcard E400P card. Our original program is based on C API similar to the functions provided in libpri.h and zap.h, so I want to use the E400P card in the following way: 1. install and
2016 Nov 22
3
[RFC] Supporting ARM's SVE in LLVM
Hi Renato, Sorry for the delay in responding. We've been busy rethinking some of our changes after the feedback we've received thus far (particularly from the devmeeting). The incremental patches will use our revised design(which should be less invasive), and I'll be updating our document to match. On 16/11/2016, 12:46, "Renato Golin" <renato.golin at linaro.org>
2019 Oct 19
3
CentOS update broke Samba
...iled to create BUILTIN\Guests group NT_STATUS_ACCESS_DENIED! Can Winbind allocate gids?" After lots of googling, I finally got the process to start properly, and (from the limited testing I can do on Saturdays) Windows clients can connect (this is the only Samba/CIFS server on the network). (FFR: I added the "username map script" and the two "idmap config A36561" stanzas in the smb.conf file below to get smbd restarted. I also needed to create a new guest user, and add "guest account = guest".) However, my Linux clients are not able to connect using CIFS. I...
2013 Apr 02
0
[LLVMdev] Instruction Implementation
Hi, > def SUBCEIL_S : FFR<0x11, 0x3, 16, (outs FGR32:$fd), (ins FGR32:$fs), > "frac.s\t$fd, $fs", [(set (f32 FGR32:$fd), (fadd (f32 FGR32:$fs ),(f32 > (ceilf FGR32:$fs))))] >; > > it makes and install correctly but when i ll try to write code to use this > instruction there is no luck. Mo...
2013 Apr 02
0
[LLVMdev] Instruction Implementation
Hi, > i ve uploaded .ll file Is that the C file that's at the end of your message? To produce a .ll file, you give clang the "-emit-llvm" option (and probably "-S"). Anyway, what I see in the C you posted is that Clang is using constant folding to avoid doing any of the operations you've requested. A better C file test would be: float foo(float d) { return d -
2013 Apr 02
1
[LLVMdev] Instruction Implementation
>I'm also a little worried that your pattern has fadd, but your C >source has a subtraction. :S i wrote it wrong the true implementation is def SUBCEIL_S : FFR<0x11, 0x3, 16, (outs FGR32:$fd), (ins FGR32:$fs), "frac.s\t$fd, $fs", [(set (f32 FGR32:$fd), (fsub (f32 FGR32:$fs ),(f32 (ceilf FGR32:$fs))))] >; I use some C,C++ code to test my backend. i use clang with those argument -m32 -emit-llvm -S -target mipsel-linux-gnu -I.. a...
2013 Apr 02
2
[LLVMdev] Instruction Implementation
Hi and thanks for answering llc works fine just does not selecting my instruction i ve uploaded .ll file how can i include this attribute "readonly" so i can see if changes the generated assembly? my code is very simple int main (){ float d, d1 ; d= 12.3; d1 = d - ceilf(d); return 0; } -- View this message in context:
2003 Feb 27
0
Update for Tru64 Unix
..._USE_CLOBBER_ARGV will work), but Tru64 5.x aligns the argv elements on 64 bit boundaries, making them look non-contiguous, when in fact they are (and overwriting the bits in between really does show up). I'll work on that and try to get a patch out soon (it'll more-or-less be based on the FFR code in sendmail that was based on what I sent them). -- Chris Adams <cmadams at hiwaay.net> Systems and Network Administrator - HiWAAY Internet Services I don't speak for anybody but myself - that's enough trouble. diff -urN openssh-SNAP-20030226/README.privsep openssh/README.priv...
2019 Dec 26
0
[PATCH 3/5] KVM: arm64: Support pvlock preempted via shared structure
...gt;> @@ -354,6 +354,11 @@ struct kvm_vcpu_arch { >> u64 last_steal; >> gpa_t base; >> } steal; >> + >> + /* Guest PV lock state */ >> + struct { >> + gpa_t base; >> + } pv; >> }; >> >> /* Pointer to the vcpu's SVE FFR for sve_{save,load}_state() */ >> @@ -515,6 +520,18 @@ static inline bool kvm_arm_is_pvtime_enabled(struct kvm_vcpu_arch *vcpu_arch) >> return (vcpu_arch->steal.base != GPA_INVALID); >> } >> >> +static inline void kvm_arm_pvlock_preempted_init(struct kvm_vcpu_a...
2019 Oct 19
0
CentOS update broke Samba
...sts group NT_STATUS_ACCESS_DENIED! Can Winbind > allocate gids?" > > After lots of googling, I finally got the process to start properly, > and (from the limited testing I can do on Saturdays) Windows clients > can connect (this is the only Samba/CIFS server on the network). (FFR: > I added the "username map script" and the two "idmap config A36561" > stanzas in the smb.conf file below to get smbd restarted.? I also > needed to create a new guest user, and add "guest account = guest".)? > However, my Linux clients are not able t...
2007 Jun 07
2
Bridged PRI calls - processor involvement?
On a zaptel TE410p, when a call is bridged PRI - PRI how much involvement does the processor have? We're now seeing chunks of missing audio and I can't tell whether this is due to a kernel upgrade or to a zaptel/libpri/asterisk upgrade. I'm not seeing missed interrupts (from a cat of the proc/zaptel files), any other ideas on how I could go about tracking this down? I'm
2019 Oct 19
2
CentOS update broke Samba
...UILTIN\Guests group NT_STATUS_ACCESS_DENIED! Can Winbind allocate gids?" >> >> After lots of googling, I finally got the process to start properly, and (from the limited testing I can do on Saturdays) Windows clients can connect (this is the only Samba/CIFS server on the network). (FFR: I added the "username map script" and the two "idmap config A36561" stanzas in the smb.conf file below to get smbd restarted.? I also needed to create a new guest user, and add "guest account = guest".) However, my Linux clients are not able to connect using CIFS.? I...
2018 Jun 12
3
[RFC][SVE] Supporting SIMD instruction sets with variable vector lengths
...fficiently (in the > limit, it seems equivalent to SSA construction). Ok; the fact that there's more instructions that can change vl and that you might need to reload it is useful to know. SVE uses predication to achieve the same via the first-faulting/no-faulting load instructions and the ffr register. I think SVE having 16 predicate registers (vs. 8 for RVV and AVX-512) has led to us using the feature quite widely with our own experiments; I'll try looking for non-predicated solutions as well when we try to expand scalable vectorization capabilities. >> Unfortunately, I can...
2019 Dec 17
10
[PATCH 0/5] KVM: arm64: vcpu preempted check support
From: Zengruan Ye <yezengruan at huawei.com> This patch set aims to support the vcpu_is_preempted() functionality under KVM/arm64, which allowing the guest to obtain the vcpu is currently running or not. This will enhance lock performance on overcommitted hosts (more runnable vcpus than physical cpus in the system) as doing busy waits for preempted vcpus will hurt system performance far
2019 Dec 17
10
[PATCH 0/5] KVM: arm64: vcpu preempted check support
From: Zengruan Ye <yezengruan at huawei.com> This patch set aims to support the vcpu_is_preempted() functionality under KVM/arm64, which allowing the guest to obtain the vcpu is currently running or not. This will enhance lock performance on overcommitted hosts (more runnable vcpus than physical cpus in the system) as doing busy waits for preempted vcpus will hurt system performance far
2006 Apr 03
18
newbie generate scaffold
Hi Guys First time on the list and pretty new to the rails way of doing things, yup I know sorry.. another newbie! anyway, apologies out of the way, this is the problem I am having... I have purchased the "Agile Development with Rails" book and have just started running through the ''Depot'' demo application. I have got to page 57... I have my project files all
2018 Jul 31
4
[RFC][SVE] Supporting SIMD instruction sets with variable vector lengths
On Tue, 31 Jul 2018 at 03:53, David A. Greene <dag at cray.com> wrote: > I wasn't talking about within an instruction but rather across > instructions in the same expression tree. Something like this would be > weird: Yes, that's what I was referring as "not in the API" therefore "user error". > The points where VL would be changed are limited and