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On Fri, 04 May 2007 14:37:53 +0200 Florian Brandner <fbrandne at mail.tuwien.ac.at> wrote: >hello, > >i've problems running the llvm-test suite using debian linux and make >3.81. it works fine on my laptop, running openSuse and make 3.81. > >i already tried to install make 3.75 and 3.79, both did not work. > >the error message...

hello, i've problems running the llvm-test suite using debian linux and make 3.81. it works fine on my laptop, running openSuse and make 3.81. i already tried to install make 3.75 and 3.79, both did not work. the error message is: make[1]: *** No rule to make target `Output/sse.expantfft.bc', needed by `Output/sse.expandfft.linked.rbc'. Stop. using make -p, i see that

Reid Spencer wrote: > Have you modified the makefile in any way? Note that sse.expantfft.bc should be sse.expandfft.bc no, did'nt change it. the typo before seems to be an error while copying from the terminal. i've cleaned everything and tried again. this is the messsage: [brandner:/localtmp/brandner/dev/llvm-test:529] make -j1 TEST=nightly 2>&1 | tee report.nightly.raw.out

Ferad Zyulkyarov wrote: > By the way. I will use the opportunity to ask you again :) I tried to > compile with gcc 4.0.4. It successfully compile LLVM but fails > compiling LLVM's gcc front end. The problem is architectural 32 and 64 > bit. The machine has intel xeon CPU that is physically 32 bit but has > 64 extension x86_64 (or something like that, I am not exactly sure). >

hi, i`m working on a machine instruction scheduler for an VLIW architecture. loads are somewhat expensive on this architecture, thus i would like to reorder unrelated loads/stores to better hide load latencies. to do this, i would need alias information on machine instructions, i.e., which machine instructions may access the same memory region. as far as i know, this is not available at the

Chris Lattner wrote: > On Wed, 16 May 2007, Florian Brandner wrote: > http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20070514/049609.html > > http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20070514/049608.html > > http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20070514/049606.html > >

Dan Gohman wrote: > On Wed, May 23, 2007 at 12:23:38AM -0700, Chris Lattner wrote: >> On Fri, 4 May 2007, Florian Brandner wrote: >>> i had a look at the SelectionDAG based schedulers. it seems that >>> aliasing loads/stores are chained together by the DAGCombiner. after >>> scheduling, when the MachineInstrs are created, the alias information >>>

hi, i'm writing a target dependent analysis on machine instruction level in llvm 2.0. the analysis needs to know if an inline assembly block reads from memory. the programmer is responsible to add 'm' constraints accordingly. i've seen the operand flags of the inline assembly SDNode and the machine instructions. but it seems that there is no difference between input and output

Pekka Jääskeläinen schrieb: > Is it somehow possible to use alias analyser data during code > generation, after instruction selection? I would need to run > the AA using MachineOperands, not Values. Is this in any way > in LLVM possible at the moment? i've been working on this (also because of a post-pass scheduler). i managed to hand the source values (values passed to the AA)

hi, the architecture that we are compiling for has a special vector shuffle instruction, which writes two successive registers (Rn and Rn+1). i have defined intrinsics to generate the instruction, and a special register class for the register pairs. in addition i have two EXTRACT operations which allow to access either the first or second subregister of a pair (using moves). the pair register

Chris Lattner wrote: > There are a couple of ways to do this. Is your scheduler a prepass > scheduler (before regalloc) or a post-pass scheduler (after regalloc)? it is a post-pass scheduler, which operates on MachineInstrs. we need to run it after register allocation to hide latencies of spill code, prolog, and epilog. > If you want to extract maximal parallelism, I assume you want a

hi, i found a problem in LLVM regarding the matching of 'Constant' nodes in the instruction selector. the testcase is for x86, but similar testcases for the other architectures (e.g. ppc) should be easy to create. i'm using the llvm-gcc 2.0 prerelease binary package. here is the testcase: int foo(int bar) { asm("movl %1, %0" : "=r"(bar) : "i"(5));

Dan Gohman wrote: > I tried out your patch on x86 and it didn't appear to need any special changes. it might be needed to look at the addressing modes of a load/store to get the right offset. but i think it should work, if the lowering does not rewrite loads/stores into custom DAG nodes. > For the [??], it looks like the IsFrameIndex isn't getting set for the first > instruction

hi, i know it took a while, but here is a patch that adds a list of source values to machine instructions. i modified the DAGISelEmiter to automatically catch regular loads/stores. custom instructions and loads/stores rewritten by the lowering pass are not automatically captured. during the instruction selection a source value operand is added to the DAG for patterns matching a load/store.

hi, Florian Brandner wrote: > Dan Gohman wrote: >> On Wed, May 23, 2007 at 12:23:38AM -0700, Chris Lattner wrote: >>> Right. The original Value*'s are preserved in the DAG, but dropped when >>> MachineInstrs are created. We could add a machineoperand to capture this >>> Value* if desired. >> Another benefit of keeping the original Value*'s