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...one to one mapping to ARM instructions. There are usually one or more instructions defined in the td file correspond to one actual ARM instruction. Thanks, David On Thu, Jun 7, 2012 at 1:27 PM, Jim Grosbach <grosbach at apple.com> wrote: > > On Jun 7, 2012, at 7:53 AM, Fan Dawei <fandawei.s at gmail.com> wrote: > > Hi Tim, > > Thanks a lot for your help! I'm very grateful. > > libc.so is a prelinked library, I'll build a non-prelinked one and have > another try. > > I'm now at the start of a binary translation project. I want to convert >...

...a clear cut thing. For example, is "add r1, r2, r3" the same ARM instruction as "add r1, r2, #4"? What is a distinct instruction and what's a variant encoding of the same instruction is often entirely a matter of convenience. -Jim On Jun 8, 2012, at 6:40 AM, Fan Dawei <fandawei.s at gmail.com> wrote: > Hi Jim, > > Thanks for reply. I'm sorry I didn't make myself clear enough. > > The MCInst created by MCDisassembler depends on the instructions defined in td files. These instructions do not have a one to one mapping to ARM instructions. There...

..., so it is bad for us. Because there is no $a, $t and $d symbols, we cannot figure out which region is arm code or thumb code statically. On Thu, Jun 7, 2012 at 8:11 PM, Tim Northover <t.p.northover at gmail.com>wrote: > Hi David, > > On Thu, Jun 7, 2012 at 10:17 AM, Fan Dawei <fandawei.s at gmail.com> wrote: > > Could you please tell me more about $a, $t and $d symbols? How these > symbols > > are used to define different regions? Where I can find this symbols in > ELF > > object file? > > At the start of each range of ARM code, an assembler or co...

On Jun 7, 2012, at 7:53 AM, Fan Dawei <fandawei.s at gmail.com> wrote: > Hi Tim, > > Thanks a lot for your help! I'm very grateful. > > libc.so is a prelinked library, I'll build a non-prelinked one and have another try. > > I'm now at the start of a binary translation project. I want to convert ARM binary...

Hi, I'm considering to use MC disassembler for ARM target in a binary translation project. However after trying some ARM binary and I find that there are a lot of instructions that the disassembler fails to to decoding. Could anyone give me some information about the maturity of ARM disassembler? Thanks! David -------------- next part -------------- An HTML attachment was scrubbed... URL:

On Jun 5, 2012, at 7:44 PM, Fan Dawei <fandawei.s at gmail.com> wrote: > Hi, > > I'm considering to use MC disassembler for ARM target in a binary translation project. However after trying some ARM binary and I find that there are a lot of instructions that the disassembler fails to to decoding. > > Could anyone give me...

...was not longer replaced by OR. Only for add+1 to or, which is correct. So now I don't understand that a option in datalyout. According doc it is alignment for aggregate type. But anyhow thanks for help and pointing me in right direction. Peter. On Wed, Apr 25, 2012 at 4:31 PM, Fan Dawei <fandawei.s at gmail.com> wrote: > Hi Peter, > > I think the problem is that you did not explicitly define stack alignment > in Z80TargetMachine.cpp > > DataLayout("e-p:16:8:8-i8:8:8-i16:8:8-i32:8:8-n8") > > Try to add S16 to the string if your stack is 2-byte aligned....

Hi David, On Thu, Jun 7, 2012 at 10:17 AM, Fan Dawei <fandawei.s at gmail.com> wrote: > Could you please tell me more about $a, $t and $d symbols? How these symbols > are used to define different regions? Where I can find this symbols in ELF > object file? At the start of each range of ARM code, an assembler or compiler should produce a "$a&q...

Hi Tim, Thanks a lot for the reply. I tested libc.so which is a shared library. llvm-objdump also report some disassemble errors. Could you please tell me more about $a, $t and $d symbols? How these symbols are used to define different regions? Where I can find this symbols in ELF object file? Thanks, David I'm now try to find a decoder of ARM instructions in oder On Thu, Jun 7, 2012

Hi llvmdev, I've noticed that there is no unary operator in LLVM. For unary operator such as Neg or Or operator, the IR builder just creates a binary operation with one dummy operand, 01823 <http://llvm.org/doxygen/classllvm_1_1BinaryOperator.html#a073c092ce74a122e898e435e60e84599> BinaryOperator <http://llvm.org/doxygen/classllvm_1_1BinaryOperator.html>

...mp in a correct way? I think that one possible reason is that llvm-objdump encounter pc relative data. I'll figure out if this is the reason. Thanks, David On Wed, Jun 6, 2012 at 1:36 PM, Evan Cheng <evan.cheng at apple.com> wrote: > > On Jun 5, 2012, at 7:44 PM, Fan Dawei <fandawei.s at gmail.com> wrote: > > > Hi, > > > > I'm considering to use MC disassembler for ARM target in a binary > translation project. However after trying some ARM binary and I find that > there are a lot of instructions that the disassembler fails to to decoding. &gt...

Hi Rotem, What do you mean by "you can use the <4 x float> type for which the vselect works". Do you mean that then back-end can correctly split the operands when it is a four elements vector? I've try that, but it still fails. On Wed, Oct 19, 2011 at 4:21 PM, Rotem, Nadav <nadav.rotem at intel.com> wrote: > This is indeed a bug. I get a different error on my

Hi Peter, I think the problem is that you did not explicitly define stack alignment in Z80TargetMachine.cpp DataLayout("e-p:16:8:8-i8:8:8-i16:8:8-i32:8:8-n8") Try to add S16 to the string if your stack is 2-byte aligned. Refer to http://llvm.org/docs/LangRef.html#datalayout . If it does not work, try to specify the layout in the input module using target layout directive. David On

Hello. I am playing with LLVM and trying to make Z80 (Zilog Z80) backend. The source code is attached. I have succesfully made some simple test. But now I have problem with ADD instruction. The source C code is: typedef struct { unsigned char id1; unsigned char id2; unsigned char id3; } testS; void simple() { testS test; test.id1 = 0x40; test.id2 = 0x80; test.id3 = 0xc0; } It

Hi llvmdev, I am still using llvm 2.9. The function addPassesToEmitMC in 3.0 takes a extra parameter to specify the raw stream for the emitter to emit code. However in 2.9, there is no such a parameter. How shall I do if want to pass a raw_stream object? llvm 2.9 // addPassesToEmitMC - Add passes to the specified pass manager to get /// machine code emitted with the MCJIT. This method returns

Hello LLVMdev, Our processor has mac (multiply and accumulate) instructions which takes the accumulator register (acc) as an implicit operand. This is different from typical three or four operands mac instructions. As an illustration, the following instructions compute a + b x c + e x f + g *h. initacc a //initialize the accumulator register fmac b c fmac e f fmac g h

For the following code fragment, ; <label>:27 ; preds = %27, %entry %28 = load volatile i32* inttoptr (i64 2149581832 to i32*), align 8 %29 = icmp slt i32 %28, 0 br i1 %29, label %27, label %loop.exit loop.exit: ; preds = %27 llc will generate following MIPS code, $BB0_1: lui $3, 32800 ori $3, $3, 1032 lw

Hi all, I want to use scalarrepl pass to eliminate the allocation of mat_alloc which is of type [4 x <4 x float>] in the following program. $cat test.ll ; ModuleID = 'test.ll' define void @main(<4 x float>* %inArg, <4 x float>* %outArg, [4 x <4 x float>]* %constants) nounwind { entry: %inArg1 = load <4 x float>* %inArg %mat_alloc = alloca [4 x <4 x

Hi LLVMdev, In the specification of llvm ir, the select operation can takes a condition of vector type, 'select' Instruction Syntax: <result> = select *selty* <cond>, <ty> <val1>, <ty> <val2> *; yields ty* *selty* is either i1 or {<N x i1>} Overview: The 'select' instruction is used to choose one value based on a condition,

Hi Chris, Thanks for your reply. You said that scalarRepl gets shy about loads and stores of the entire aggregate. Then I use a test case: ; ModuleID = 'test1.ll' define i32 @fun(i32* nocapture %X, i32 %i) nounwind uwtable readonly { %stackArray = alloca <4 x i32> %XC = bitcast i32* %X to <4 x i32>* %arrayVal = load <4 x i32>* %XC store <4 x i32>