search for: f32imm

I tried to generate pattern for instruction which transports floating point immediate to a floating point register. def MOVF32fk : InstTCE<(outs F32Regs:$dst), (ins f32imm:$val), "$val -> $dst;", [(set F32Regs:$dst, (f32 imm:$val))]>; This causes an type contradiction: /home/hkultala26/src/devel/tce/src/applibs/LLVMBackend/plugin//TCEInstrInfo.td:109:1: error: In MOVF32fk: Type inference contradiction found, 'f32...

...> def rr32 : InstPTX<(outs RegF32:$d), > (ins RndMode:$r, RegF32:$a, RegF32:$b), > !strconcat(opcstr, "$r.f32\t$d, $a, $b"), []>; > def ri32 : InstPTX<(outs RegF32:$d), > (ins RndMode:$r, RegF32:$a, f32imm:$b), > !strconcat(opcstr, "$r.f32\t$d, $a, $b"), []>; > def rr64 : InstPTX<(outs RegF64:$d), > (ins RndMode:$r, RegF64:$a, RegF64:$b), > !strconcat(opcstr, "$r.f64\t$d, $a, $b"), []>; > de...

...essful so far. Here is an example of something I have tried. It fails to compile with tablegen, but I hope it can help demonstrate what I am trying to do: def F32Node : PatLeaf<(vt), [{return N->getVT() == MVT::f32;}]>; def F32Op : Operand <f32> { let MIOperandInfo = (ops GPR, f32imm); } def ADD : InstAMD < (outs GPR:$dst), (ins F32Op:$src0, F32Op:$src1), "ADD $dst, $src0, $src1"), [(set GPR:$dst, (fadd F32Node:$src0, F32Node:$src1))] >; Is what I am trying to do possible with tablegen, and if so what is the best way...

...P<string opcstr> { def rr32 : InstPTX<(outs RegF32:$d), (ins RndMode:$r, RegF32:$a, RegF32:$b), !strconcat(opcstr, "$r.f32\t$d, $a, $b"), []>; def ri32 : InstPTX<(outs RegF32:$d), (ins RndMode:$r, RegF32:$a, f32imm:$b), !strconcat(opcstr, "$r.f32\t$d, $a, $b"), []>; def rr64 : InstPTX<(outs RegF64:$d), (ins RndMode:$r, RegF64:$a, RegF64:$b), !strconcat(opcstr, "$r.f64\t$d, $a, $b"), []>; def ri64 : InstPTX<(outs...

...{ > def rr32 : InstPTX<(outs RegF32:$d), > (ins RndMode:$r, RegF32:$a, RegF32:$b), > binary_pattern<opcstrm "f32">.pattern, []>; > def ri32 : InstPTX<(outs RegF32:$d), > (ins RndMode:$r, RegF32:$a, f32imm:$b), > binary_pattern<opcstrm "f32">.pattern, []>; > def rr64 : InstPTX<(outs RegF64:$d), > (ins RndMode:$r, RegF64:$a, RegF64:$b), > binary_pattern<opcstrm "f64">.pattern, []>; > d...

...oo limiting. In this example: (Equivalent TableGen code with a for-loop) ---------------------------------------- multiclass PTX_FLOAT_4OP<string opcstr, SDNode opnode1, SDNode opnode2> { for nbit = [32, 32, 64, 64], op_suffix = [r, i, r, i], op_type = [RegF32, f32imm, RegF64, f64imm], op_node_type = [RegF32, fpimm, RegF64, fpimm] in { def rr#op_suffix#nbit : InstPTX<(outs RegF#nbit:$d), (ins RegF#nbit:$a, RegF#nbit:$b, #op_type:$c), !strconcat(opcstr, ".f#nbit\t$d, $a, $b, $c"), [(set...

...), [(set RegF32:$d, (opnode2 (opnode1 RegF32:$a, RegF32:$b), RegF32:$c))]>; def rri32 : InstPTX<(outs RegF32:$d), (ins RegF32:$a, RegF32:$b, f32imm:$c), !strconcat(opcstr, ".f32\t$d, $a, $b, $c"), [(set RegF32:$d, (opnode2 (opnode1 RegF32:$a, RegF32:$b), fpimm:$c))]>; def rrr64 :...

...mething I have > tried. It fails to compile with tablegen, but I hope it can help > demonstrate what I am trying to do: > > > def F32Node : PatLeaf<(vt), [{return N->getVT() == MVT::f32;}]>; > > def F32Op : Operand <f32> { > let MIOperandInfo = (ops GPR, f32imm); > } > > def ADD : InstAMD < > (outs GPR:$dst), > (ins F32Op:$src0, F32Op:$src1), > "ADD $dst, $src0, $src1"), > [(set GPR:$dst, (fadd F32Node:$src0, F32Node:$src1))] > >; > > Is what I am trying to do possi...

Jakob Stoklund Olesen <jolesen at apple.com> writes: > The TableGen language seems to be growing Lisp macros from two > different directions. > > Che-Liang Chiou added a preprocessor with for loops, and David Greene > added multidefs. > > It seems that some kind of macro facility is needed, perhaps we should > discuss what it is supposed to look like? Don't

The TableGen language seems to be growing Lisp macros from two different directions. Che-Liang Chiou added a preprocessor with for loops, and David Greene added multidefs. It seems that some kind of macro facility is needed, perhaps we should discuss what it is supposed to look like? /jakob

Evan Cheng <evan.cheng at apple.com> writes: > David, we cannot accept the 'multidef' keyword. Please revert it. Working on it now. > We appreciate you thinking ahead about MIC, but we are against the > massive refactoring and complicated abstraction scheme. We'll never > accept those patches. How about a less massive and complicated scheme? I think we can make

...; > (Equivalent TableGen code with a for-loop) > ---------------------------------------- > multiclass PTX_FLOAT_4OP<string opcstr, SDNode opnode1, SDNode opnode2> { > for nbit = [32, 32, 64, 64], > op_suffix = [r, i, r, i], > op_type = [RegF32, f32imm, RegF64, f64imm], > op_node_type = [RegF32, fpimm, RegF64, fpimm] in { > def !strconcat(!strconcat("rr", !cast<string>(op_suffix)), "nbit") > [...] > } > } > > Yes, it's a bit more verbose but also more flexible in what you can do...

You can tell LLVM that you have "sign extended" setCC results (all ones). Dan On Nov 18, 2008, at 5:33 PM, Eli Friedman wrote: > On Tue, Nov 18, 2008 at 1:56 PM, Villmow, Micah > <Micah.Villmow at amd.com> wrote: >> The IR produces correct results, but my backend does not and the >> only thing >> I can think of is that the IR is treating the

...: InstPTX<(outs RegF32:$d), >>                     (ins RndMode:$r, RegF32:$a, RegF32:$b), >>                     binary_pattern<opcstrm "f32">.pattern, []>; >>  def ri32 : InstPTX<(outs RegF32:$d), >>                     (ins RndMode:$r, RegF32:$a, f32imm:$b), >>                     binary_pattern<opcstrm "f32">.pattern, []>; >>  def rr64 : InstPTX<(outs RegF64:$d), >>                     (ins RndMode:$r, RegF64:$a, RegF64:$b), >>                     binary_pattern<opcstrm "f64">.pattern,...

...oo limiting. In this example: (Equivalent TableGen code with a for-loop) ---------------------------------------- multiclass PTX_FLOAT_4OP<string opcstr, SDNode opnode1, SDNode opnode2> { for nbit = [32, 32, 64, 64], op_suffix = [r, i, r, i], op_type = [RegF32, f32imm, RegF64, f64imm], op_node_type = [RegF32, fpimm, RegF64, fpimm] in { def rr#op_suffix#nbit : InstPTX<(outs RegF#nbit:$d), (ins RegF#nbit:$a, RegF#nbit:$b, #op_type:$c), !strconcat(opcstr, ".f#nbit\t$d, $a, $b, $c"), [(set...