search for: i32imm

Hi, That's what the DecoderMethod is for. Similarly ParserMatchClass for the asm parser and PrintMethod for the asm printer: def CondCodeOperand : AsmOperandClass { let Name = "CondCode"; } def pred : PredicateOperand<OtherVT, (ops i32imm, i32imm), (ops (i32 14), (i32 zero_reg))> { let PrintMethod = "printPredicateOperand"; let ParserMatchClass = CondCodeOperand; let DecoderMethod = "DecodePredicateOperand"; } James On Mon, 14 Dec 2015 at 13:44 Sky Flyer <skylake...

...planned to do but just wasn't sure. Thanks for that. On Mon, Dec 14, 2015 at 11:52 AM, James Molloy <james at jamesmolloy.co.uk> wrote: > Hi, > > You can't nest operands like that - it must be a flattened list. So: > > def *Xpred* : PredicateOperand<OtherVT, (ops *i32imm, i32imm*, i32imm), > (ops (i32 14), (i32 zero_reg))> {...} > > On Mon, 14 Dec 2015 at 10:21 Sky Flyer via llvm-dev < > llvm-dev at lists.llvm.org> wrote: > >> Hi All, >> >> In ARMInstFormats.td predicate is defined this way: >> >> >> >&...

Hi All, In ARMInstFormats.td predicate is defined this way: *def pred : PredicateOperand<OtherVT, (ops i32imm, i32imm),* *(ops (i32 14), (i32 zero_reg))> {...}* I use the same definition in my code. But I have another version of predicate which is exactly the same but it is a condition code plus a quantifier! (e.g. Xpred = (pred + i32imm)). I was wondering how we can define a sub sub operand, somethi...

I want to generate the instruction like addi 40, r3 ! i.e. r3 = r3 + 40 The format i wrote is def ADDI : F1<opcode, (outs IntRegs:$dst), (ins IntRegs:$dst, i32imm:$imm) "addi $imm, $dst", [(set $IntRegs:$dst, (add $IntRegs:$dst, i32imm:$c))] but it is not compiling. what should be the format. vikram -- View this message in context: http://llvm.1065342.n5.nabble.com/Generate-addi-40-r3-instruction-...

...NPOptInGlue, SDNPOutGlue, SDNPVariadic]>; def MYret : SDNode<"MYISD::RET_FLAG", SDTNone, [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; let hasCtrlDep = 1, hasSideEffects = 1 in { def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2), [(MYCallseqStart timm:$amt1, timm:$amt2)]>; def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2), [(MYCallseqEnd timm:$amt1, timm:$amt2)]>; } def: Pat<(MYret), (JMP_Ret (...

Hi all, what is exactly "zero_reg"? from ARMInstFromats.td: *def pred : PredicateOperand<OtherVT, (ops i32imm, i32imm), (ops (i32 14), (i32 zero_reg))> {...}* I thought zero_reg can be replace by a random name like (alu_stat_reg for alu state register) but when I compiled it, I figure out that zero_reg is a predefined variable. Can someone please give me more information about zero_reg and if possible...

...'m trying to figure out how to add the instructions required for llvm.atomic.cmp.swap.i32 on PowerPC. I figured out LWARX (patch attached) but the other two (CMP_UNRESw and STWCX) require multiple instructions: let Defs = [CR0] in { def STWCX : Pseudo<(outs), (ins GPRC:$rS, memrr:$dst, i32imm:$label), "stwcx. $rS, $dst\n\tbne- La${label}_entry\nLa${label}_exit:", [(PPCstcx GPRC:$rS, xoaddr:$dst, imm:$label)]>; def CMP_UNRESw : Pseudo<(outs), (ins GPRC:$rA, GPRC:$rB, i32imm:$label), "cmpw $rA, $...

...assembler will be emitting the // .debug_line table automatically. if (MAI->hasDotLocAndDotFile()) return; Previously .loc directives are printed by selecting ISD::DEBUG_LOC nodes to pseudo instructions which print as the directive. For example: def DWARF_LOC : Pseudo<(outs), (ins i32imm:$line, i32imm:$col, i32imm:$file), ".loc $file, $line, $col", [(dwarf_loc (i32 imm:$line), (i32 imm:$col), (i32 imm:$file))]>; ISD::DEBUG_LOC nodes are produced when debug stoppoints are expanded. However debug stoppoints are no longer produced by the frontend...

It seems to me that emitting DWARF line number information using .loc directives is currently broken. CellSPU is currently the only in tree target that sets HasDotLocAndDotFile in its MCAsmInfo and I can't get it to produce any line number information. Is this a known issue? I understand that there are lots of changes going on in this area. Any idea what it would take to fix? -- Richard

...r by 'amount' (i.e. sp = sp + amount). During assembly generation, the string that gets emitted is "ADS $SP" rather than "ADS 10", for example, if I want to increment it by 10. Can somebody show me what I'm doing wrong? Thanks. def ADS: F_J<0b100001,(outs),(ins i32imm:$amount),"ADS $amount",[(set SP, (add SP, i32imm:$amount))] > { bits<10> amount; let Inst{9-0} = amount; let isReMaterializable = 1; let mayLoad = 0; let mayStore = 0; let Defs = [SP]; let Uses = [SP]; } -------------- nex...

Hi, I have reworked my previous example and got something which is accepted by tblgen: let isCall = 1, Defs = [R0, R1, R2, R3, R12, LR, D0, D1, D2, D3, D4, D5, D6, D7, CPSR] in { def ARM_ATOMIC_CMP_SWAP : ABXI<0b1011, (outs GPR:$dst), (ins i32imm:$ptr, i32imm:$old, i32imm:$new), "do_something", [(set GPR:$dst, (atomic_cmp_swap_32 globaladdr:$ptr, imm:$old, imm:$new))]>; } What I want to achieve first is that llc picks this definition when it finds an occurance of the @atomic.cmp.swap.i32...

...PVariadic]>; > def MYret : SDNode<"MYISD::RET_FLAG", SDTNone, > [SDNPHasChain, SDNPOptInGlue, > SDNPVariadic]>; > > let hasCtrlDep = 1, hasSideEffects = 1 in { > def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2), > [(MYCallseqStart timm:$amt1, > timm:$amt2)]>; > def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2), > [(MYCallseqEnd timm:$amt1, timm:$amt2)]>; > } > >...

...RET_FLAG", SDTNone, [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; let hasCtrlDep = 1, hasSideEffects = 1, isCodeGenOnly = 1, Defs = [SP], Uses = [SP] in { def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2), [(MyCallseqStart timm:$amt1, timm:$amt2)]>; def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2), [(MyCallseqEnd timm:$amt1, timm:$amt2)]>; } def Custo...

...ike comparisons which are not supported for address regs). Is it still possible to get ride of this with register classes ? It should be, yes. For a contrived example of a simple add-immediate instruction for each: def ADD_address_reg: myBaseInstrClass<(outs ADDR_REG:$dst), (ins ADDR_REG:$src, i32imm:$imm), [(set ADDR_REG:$dst, (add ADDR_REG:$dst, i32imm:$imm)]>; def ADD_general_reg: myBaseInstrClass<(outs GPR:$dst), (ins GPR:$src, i32imm:$imm), [(set GPR:$dst, (add GPR:$dst, i32imm:$imm)]>; Likewise, other operations that can target either register class should have a variant for ea...

Hi, I am missing atomic operations support for the ARM backend (see PR #3887) and started trying to implement them. Since this is the first time that I work on such stuff (and llvm) I am going to take the supposedly easy route and provide an implementation that will work on Linux systems. This involves calling a special function which the kernel handles itself. Details here:

.... During assembly generation, the string that gets emitted is "ADS $SP" rather than "ADS 10", for example, if I want to increment it by 10. >> >> Can somebody show me what I'm doing wrong? >> Thanks. >> >> def ADS: F_J<0b100001,(outs),(ins i32imm:$amount),"ADS $amount",[(set SP, (add SP, i32imm:$amount))] > { >> >> bits<10> amount; >> >> let Inst{9-0} = amount; >> let isReMaterializable = 1; >> let mayLoad = 0; >> let mayStore = 0; >>...

...el.inc, I see: /*56478*/ /*SwitchOpcode*/ 13, TARGET_VAL(ISD::GlobalAddress),// ->56494 /*56481*/ OPC_RecordNode, // #0 = $src /*56482*/ OPC_CheckType, MVT::i32, /*56484*/ OPC_CheckPatternPredicate, 4, // (!Subtarget->isThumb()) /*56486*/ OPC_MorphNodeTo, TARGET_VAL(ARM::MOVi32imm), 0, 1/*#VTs*/, MVT::i32, 1/*#Ops*/, 0, // Src: (globaladdr:i32):$src - Complexity = 3 // Dst: (MOVi32imm:i32 (globaladdr:i32):$src) The first lines are fairly unimportant, but the last two show what the DAG thinks it's doing and make it clear why...

Hi Jim, Thanks for your response. Le 06/03/2012 22:54, Jim Grosbach a écrit : > Hi Ivan, > On Mar 3, 2012, at 4:48 AM, Ivan Llopard<ivanllopard at gmail.com> wrote: > >> Hi, >> >> I'm facing a problem in llvm while porting it to a new target and I'll >> need some support. >> We have 2 kind of register, one for general purposes (i.e.

...nstrInfo class The compiler generates the some code as before, but that seems to be ok, because I haven't used ptr_rc yet. 4) I changed the address mode MEMri: def MEMri : Operand<iPTR> { let PrintMethod = "printMemOperand"; // was: let MIOperandInfo = (ops IntRegs, i32imm); let MIOperandInfo = (ops ptr_rc, i32imm); } for the C code int c; void f(void) { c = 4711; } I get the error message: Register class of operand and regclass of use don't agree! Operand = 0 Op->Val = 0x42b08d60: i32 = SETHIi 0x42b08d00 MI = STri %reg1026 VReg = 1026 VReg RegCla...

...ns which are not supported for address regs). Is it still possible to get ride of this with register classes ? > It should be, yes. For a contrived example of a simple add-immediate instruction for each: > > def ADD_address_reg: myBaseInstrClass<(outs ADDR_REG:$dst), (ins ADDR_REG:$src, i32imm:$imm), [(set ADDR_REG:$dst, (add ADDR_REG:$dst, i32imm:$imm)]>; > def ADD_general_reg: myBaseInstrClass<(outs GPR:$dst), (ins GPR:$src, i32imm:$imm), [(set GPR:$dst, (add GPR:$dst, i32imm:$imm)]>; > > Likewise, other operations that can target either register class should have a...