Displaying 4 results from an estimated 4 matches for "extloadi8".
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zextloadi8
2016 Jul 29
2
Help with ISEL matching for an SDAG
...BUILD_VECTOR t16, t16, t16, t16, t16, t16, t16, t16, t16,
t16, t16, t16, t16, t16, t16, t16
t11: ch,glue = CopyToReg t0, Register:v16i8 %V2, t15
t12: ch = PPCISD::RET_FLAG t11, Register:v16i8 %V2, t11:1
and the following pattern that I'd like to match:
def ScalarLoads {
dag Li8 = (i32 (extloadi8 xoaddr:$src));
}
def : Pat<(v16i8 (build_vector ScalarLoads.Li8, ScalarLoads.Li8,
ScalarLoads.Li8, ScalarLoads.Li8,
ScalarLoads.Li8, ScalarLoads.Li8,
ScalarLoads.Li8, ScalarLoads.Li8,...
2008 Nov 10
2
[LLVMdev] Load/Store issues: tablegen/customization?
I've been running into two issues with load/store handling:
(1) is that tablegen doesn't seem to handle the two predicates that
get attached to my instructions. The first is the predicate in
TargetSelectionDAG.td, identifying a load node as, say, extloadi8. The
second is my identification of the load as having a particular address
space (need different instructions for different address spaces).
In the tablegen generated code, only one predicate is tested. Anybody
seen anything similar to this (i.e. is this a known issue)? Do people
have exp...
2008 Nov 11
0
[LLVMdev] Load/Store issues: tablegen/customization?
...el M Gessel wrote:
> I've been running into two issues with load/store handling:
>
> (1) is that tablegen doesn't seem to handle the two predicates that
> get attached to my instructions. The first is the predicate in
> TargetSelectionDAG.td, identifying a load node as, say, extloadi8. The
> second is my identification of the load as having a particular address
> space (need different instructions for different address spaces).
>
> In the tablegen generated code, only one predicate is tested. Anybody
> seen anything similar to this (i.e. is this a known issue)? Do...
2012 Apr 19
0
[LLVMdev] Target Dependent Hexagon Packetizer patch
...edComplexity = 10, isPredicable = 1 in
>> def LDrib_indexed_V4 : LDInst<(outs IntRegs:$dst),
>> (ins IntRegs:$src1, IntRegs:$src2),
>> "$dst=memb($src1+$src2<<#0)",
>> - [(set IntRegs:$dst, (sextloadi8 (add IntRegs:$src1,
>> - IntRegs:$src2)))]>,
>> + [(set (i32 IntRegs:$dst),
>> + (i32 (sextloadi8 (add (i32 IntRegs:$src1),
>> +...