Displaying 2 results from an estimated 2 matches for "externalsym".
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texternalsym
2009 Mar 15
5
[LLVMdev] Overlapping register classes
...ork on all registers:
def GR : RegisterClass<"Bfin", [i32], 32,
[R0, R1, R2, R3, R4, R5, R6, R7,
P0, P1, P2, P3, P4, P5, SP, FP,
I0, I1, I2, I3, M0, M1, M2, M3,
B0, B1, B2, B3, L0, L1, L2, L3]>;
For instance, I can load an arbitrary 32-bit constant or
globaladdr/externalsym into any register:
def LOAD32imm: Pseudo<(outs GR:$dst), (ins i32imm:$src),
"$dst.H = HI($src); $dst.L = LO($src);",
[(set GR:$dst, imm:$src)]>;
I think I am stretching the code generator beyond its capability by
doing this. As far as I...
2009 Mar 16
0
[LLVMdev] Overlapping register classes
...: RegisterClass<"Bfin", [i32], 32,
> [R0, R1, R2, R3, R4, R5, R6, R7,
> P0, P1, P2, P3, P4, P5, SP, FP,
> I0, I1, I2, I3, M0, M1, M2, M3,
> B0, B1, B2, B3, L0, L1, L2, L3]>;
>
> For instance, I can load an arbitrary 32-bit constant or
> globaladdr/externalsym into any register:
>
> def LOAD32imm: Pseudo<(outs GR:$dst), (ins i32imm:$src),
> "$dst.H = HI($src); $dst.L = LO($src);",
> [(set GR:$dst, imm:$src)]>;
>
> I think I am stretching the code generator beyond its capability b...