search for: texternalsym

...(outs), (ins calltarget:$target, variable_ops), "bl $target", [(XCoreBranchLink immU20:$target)]>; def : Pat<(XCoreBranchLink tglobaladdr:$addr), (BL_lu10 tglobaladdr:$addr)>; def : Pat<(XCoreBranchLink texternalsym:$addr), (BL_lu10 texternalsym:$addr)>; is necessary. Are the Pat<> s just 'casting' tglobaladdr:$addr and texternalsym:$addr to an immU20 to force a match ? I'm guessing similar Pat<> 's aren't required for the BL_u10/immU10 cases because they match without a...

...(ins calltarget:$target, variable_ops), > "bl $target", > [(XCoreBranchLink immU20:$target)]>; > > def : Pat<(XCoreBranchLink tglobaladdr:$addr), (BL_lu10 > tglobaladdr:$addr)>; > def : Pat<(XCoreBranchLink texternalsym:$addr), (BL_lu10 > texternalsym:$addr)>; > > is necessary. Are the Pat<> s just 'casting' tglobaladdr:$addr and > texternalsym:$addr to an immU20 to force a match ? There is no casting going on, there are just 3 separate patterns all which select to the BL_lu10 instr...

...;; def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)), (MOV64ri64i32 tglobaladdr :$dst)>, Requires<[SmallCode]>; +def : Pat<(i64 (X86Wrapper tglobaltlsaddr :$dst)), + (MOV64ri32 tglobaltlsaddr :$dst)>, Requires<[SmallCode]>; def : Pat<(i64 (X86Wrapper texternalsym:$dst)), (MOV64ri64i32 texternalsym:$dst)>, Requires<[SmallCode]>; def : Pat<(i64 (X86Wrapper tblockaddress:$dst)), Unfortunately, I am 100% confident with this modification since I am not an expert of LLVM and I doubt a bit about the conversion for 32 bit to 64bit. If...

...(i64 (X86Wrapper tglobaladdr :$dst)), > (MOV64ri64i32 tglobaladdr :$dst)>, Requires<[SmallCode]>; > +def : Pat<(i64 (X86Wrapper tglobaltlsaddr :$dst)), > + (MOV64ri32 tglobaltlsaddr :$dst)>, Requires<[SmallCode]>; > def : Pat<(i64 (X86Wrapper texternalsym:$dst)), > (MOV64ri64i32 texternalsym:$dst)>, Requires<[SmallCode]>; > def : Pat<(i64 (X86Wrapper tblockaddress:$dst)), > > Unfortunately, I am 100% confident with this modification since I am not an expert of LLVM and I doubt a bit about the conversion for 32 bi...

...39;m trying following: def CustomOpParams : SDTypeProfile<0,2,[]>; def customop : SDNode<"ISD::INTRINSIC_VOID", CustomOpParams>; def : Pat<(customop tglobaladdr:$dst,iPTR:$vararg), (int_tce_customop tglobaladdr:$dst, iAny:$vararg)>; def : Pat<(call texternalsym:$dst,iAny:$vararg), (int_tce_customop texternalsym:$dst, iAny:$vararg)>; but compilation gives following error: isVoid:void anonymous.52: (intrinsic_void:void 197:iPTR, (tglobaladdr:iPTR):$dst, isVoid:void) /home/elhigu/llvm-install/llvm/Release/bin/tblgen: In anonymous.52: T...

...globaladdr :$dst)), >> (MOV64ri64i32 tglobaladdr :$dst)>, Requires<[SmallCode]>; >> +def : Pat<(i64 (X86Wrapper tglobaltlsaddr :$dst)), >> + (MOV64ri32 tglobaltlsaddr :$dst)>, Requires<[SmallCode]>; >> def : Pat<(i64 (X86Wrapper texternalsym:$dst)), >> (MOV64ri64i32 texternalsym:$dst)>, Requires<[SmallCode]>; >> def : Pat<(i64 (X86Wrapper tblockaddress:$dst)), >> >> Unfortunately, I am 100% confident with this modification since I am not an expert of LLVM and I doubt a bit about the con...

On 25 Jul 2012, at 04:49, Paul Shortis wrote: > Hello, > > I'm considering creating an LLVM backend for a 16 bit processor and > modelling it around the (experimental) MSP430 back end. > > When reviewing MSP430InstrInfo.td I see > > def MSP430Wrapper : SDNode<"MSP430ISD::Wrapper", SDT_MSP430Wrapper>; > > and can see in MSP430ISelLowering.cpp

Hello, I'm considering creating an LLVM backend for a 16 bit processor and modelling it around the (experimental) MSP430 back end. When reviewing MSP430InstrInfo.td I see def MSP430Wrapper : SDNode<"MSP430ISD::Wrapper", SDT_MSP430Wrapper>; and can see in MSP430ISelLowering.cpp that ISD::GlobalAddress: ISD::BlockAddress: ISD::ExternalSymbol all get lowered to

...gt;>> (MOV64ri64i32 tglobaladdr :$dst)>, Requires<[SmallCode]>; >>> +def : Pat<(i64 (X86Wrapper tglobaltlsaddr :$dst)), >>> + (MOV64ri32 tglobaltlsaddr :$dst)>, Requires<[SmallCode]>; >>> def : Pat<(i64 (X86Wrapper texternalsym:$dst)), >>> (MOV64ri64i32 texternalsym:$dst)>, Requires<[SmallCode]>; >>> def : Pat<(i64 (X86Wrapper tblockaddress:$dst)), >>> >>> Unfortunately, I am 100% confident with this modification since I am not an expert of LLVM and I do...

...AG & DAG) const; Index: lib/Target/PowerPC/PPCInstr64Bit.td =================================================================== --- lib/Target/PowerPC/PPCInstr64Bit.td (revision 52957) +++ lib/Target/PowerPC/PPCInstr64Bit.td (working copy) @@ -116,23 +116,34 @@ def : Pat<(PPCcall_ELF (i64 texternalsym:$dst)), (BL8_ELF texternalsym:$dst)>; -// Atomic operations. -def LDARX : Pseudo<(outs G8RC:$rD), (ins memrr:$ptr, i32imm:$label), - "\nLa${label}_entry:\n\tldarx $rD, $ptr", - [(set G8RC:$rD, (PPClarx xoaddr:$ptr, imm:$label))]>;...

PPCTargetLowering::EmitInstrWithCustomInserter has a reference to the current MachineFunction for other purposes. Can you use MachineFunction::getRegInfo instead? Dan On Jul 8, 2008, at 1:56 PM, Gary Benson wrote: > Would it be acceptable to change MachineInstr::getRegInfo from private > to public so I can use it from > PPCTargetLowering::EmitInstrWithCustomInserter? > >

...AG & DAG) const; Index: lib/Target/PowerPC/PPCInstr64Bit.td =================================================================== --- lib/Target/PowerPC/PPCInstr64Bit.td (revision 53464) +++ lib/Target/PowerPC/PPCInstr64Bit.td (working copy) @@ -116,23 +116,34 @@ def : Pat<(PPCcall_ELF (i64 texternalsym:$dst)), (BL8_ELF texternalsym:$dst)>; -// Atomic operations. -def LDARX : Pseudo<(outs G8RC:$rD), (ins memrr:$ptr, i32imm:$label), - "\nLa${label}_entry:\n\tldarx $rD, $ptr", - [(set G8RC:$rD, (PPClarx xoaddr:$ptr, imm:$label))]>;...

Hi Gary, This does not patch cleanly for me (PPCISelLowering.cpp). Can you prepare a updated patch? Thanks, Evan On Jul 10, 2008, at 11:45 AM, Gary Benson wrote: > Cool, that worked. New patch attached... > > Cheers, > Gary > > Evan Cheng wrote: >> Just cast both values to const TargetRegisterClass*. >> >> Evan >> >> On Jul 10, 2008, at 7:36

Just cast both values to const TargetRegisterClass*. Evan On Jul 10, 2008, at 7:36 AM, Gary Benson wrote: > Evan Cheng wrote: >> How about? >> >> const TargetRegisterClass *RC = is64Bit ? &PPC:GPRCRegClass : >> &PPC:G8RCRegClass; >> unsigned TmpReg = RegInfo.createVirtualRegister(RC); > > I tried something like that yesterday: > > const

Evan Cheng wrote: > How about? > > const TargetRegisterClass *RC = is64Bit ? &PPC:GPRCRegClass : > &PPC:G8RCRegClass; > unsigned TmpReg = RegInfo.createVirtualRegister(RC); I tried something like that yesterday: const TargetRegisterClass *RC = is64bit ? &PPC::GPRCRegClass : &PPC::G8RCRegClass; but I kept getting this error no matter how I arranged it:

You need to insert new basic blocks and update CFG to accomplish this. There is a hackish way to do this right now. Add a pseudo instruction to represent this operation and mark it usesCustomDAGSchedInserter. This means the intrinsic is mapped to a single (pseudo) node. But it is then expanded into instructions that can span multiple basic blocks. See

...AG & DAG) const; Index: lib/Target/PowerPC/PPCInstr64Bit.td =================================================================== --- lib/Target/PowerPC/PPCInstr64Bit.td (revision 52957) +++ lib/Target/PowerPC/PPCInstr64Bit.td (working copy) @@ -116,23 +116,34 @@ def : Pat<(PPCcall_ELF (i64 texternalsym:$dst)), (BL8_ELF texternalsym:$dst)>; -// Atomic operations. -def LDARX : Pseudo<(outs G8RC:$rD), (ins memrr:$ptr, i32imm:$label), - "\nLa${label}_entry:\n\tldarx $rD, $ptr", - [(set G8RC:$rD, (PPClarx xoaddr:$ptr, imm:$label))]>;...

Would it be acceptable to change MachineInstr::getRegInfo from private to public so I can use it from PPCTargetLowering::EmitInstrWithCustomInserter? Cheers, Gary Evan Cheng wrote: > Look for createVirtualRegister. These are examples in > PPCISelLowering.cpp. > > Evan > On Jul 8, 2008, at 8:24 AM, Gary Benson wrote: > > > Hi Evan, > > > > Evan Cheng wrote:

Chris Lattner wrote: > On Jun 27, 2008, at 8:27 AM, Gary Benson wrote: > > def CMP_UNRESw : Pseudo<(outs), (ins GPRC:$rA, GPRC:$rB, i32imm: > > $label), > > "cmpw $rA, $rB\n\tbne- La${label}_exit", > > [(PPCcmp_unres GPRC:$rA, GPRC:$rB, imm: > > $label)]>; > > } > > > > ...and

...AG & DAG) const; Index: lib/Target/PowerPC/PPCInstr64Bit.td =================================================================== --- lib/Target/PowerPC/PPCInstr64Bit.td (revision 52957) +++ lib/Target/PowerPC/PPCInstr64Bit.td (working copy) @@ -116,23 +116,35 @@ def : Pat<(PPCcall_ELF (i64 texternalsym:$dst)), (BL8_ELF texternalsym:$dst)>; -// Atomic operations. -def LDARX : Pseudo<(outs G8RC:$rD), (ins memrr:$ptr, i32imm:$label), - "\nLa${label}_entry:\n\tldarx $rD, $ptr", - [(set G8RC:$rD, (PPClarx xoaddr:$ptr, imm:$label))]>;...