search for: expandintegerresults

I tried to build VMKit on an ARM device today (a Sheevaplug - armv5te) (native, not cross compiled), and got this error: llvm[3]: Building LLVM assembly with /home/debio/build/vmkit-build/vmkit/lib/Mvm/Runtime/LLVMAssembly.ll /home/debio/build/vmkit-build/vmkit/lib/Mvm/Runtime/LLVMAssembly64.ll ExpandIntegerResult #0: 0x16fbf88: i64,ch = AtomicCmpSwap 0x16e8d84, 0x16fbf00, 0x16fc3c8,

...the return type (i64) is not legal, LLVM ends up calling into ReplaceNodeResults(). ReplaceNodeResults() has the restriction that the result has to have the same number of values and types. This forces the lowering function to return a target defined custom i64 node. At the next legalization cycle ExpandIntegerResults() is called to expand this node causing an assert because getOperationAction doesn't operate on custom nodes. Am I doing something wrong? My goal is to provide an expansion for 64-bit division that unfortunately uses branches for a target that doesn't support 64-bit integers. Thanks, Javi...

Hello, On Fri, 22 Feb 2013 16:50:39 +0400 Anton Korobeynikov <anton at korobeynikov.info> wrote: > Hello > > > I'm trying to understand how fitting source integer type width into > > target machine register width happens. My reading on LLVM > > codegeneration topics (few megabytes) so far didn't have this topic > > mentioned explicitly. > This is

hi, does someone notice that llc options "-march=hexagon" and "-march-sparcv9" do not work well under llvm 3.1? Following is a brief description: (1) test.c file int cmp(int i, int j) { return (i>j)?1:0; } (2) test.ll file (clang -emit-llvm test.c -S -o test.ll) ; ModuleID = 'test.c' target datalayout =

Hi, I'm trying to use llvm/clang to cross compile to sparcv9. The following works with a -march=sparc, but yields errors for sparcv9. Are there some other flags that need to be specified? Thanks, Tarun > clang -m64 -emit-llvm test.c -c -o test.bc > llc -march=sparcv9 test.bc -o hello.s ExpandIntegerResult #0: 0x8a6c478: i64 = GlobalAddress<[4 x i8]* @.str> 0 [ORD=1] [ID=0] Do

Hi, I'm stumped by how to handle fpowi. Here is the context: my architecture has i64, f32, and f64 registers. No i32. For calls & returns, we promote i32 to i64. There is no support in the architecture to perform fpowi - it has to go through the runtime. I'm using gfortran + dragonegg + llvm3.4 to generate .ll files via plugin. The fortran expression REAL = REAL ** INTEGER*4

sorry, llc -march=hexagon -mcpu=hexagonv2 test.ll -o test.s works. 2012/7/3 Triple Yang <triple.yang at gmail.com>: > hi, > > does someone notice that llc options "-march=hexagon" and > "-march-sparcv9" do not work well under llvm 3.1? > > Following is a brief description: > (1) test.c file > > int cmp(int i, int j) { > return

Hi, When expanding multiply operation in LegalizeTypes LLVM generates some nodes such as UMUL_LOHI (please refer file LegalizeIntegerTypes.cpp - function - ExpandIntegerResult). However while lowering this operation in LegalizeDAG (please refer file LegalizeDAG.cpp - function - LegalizeOp) the comment says "These nodes will only be produced by target-specific lowering.....".

See X86InstrInfo.td let usesCustomInserter = 1, isTwoAddress = 0, Defs = [EFLAGS] in def CMOV_GR8 : I<0, Pseudo, This creates a CMOV_GR8 pseudo instruction at isel time which can be expanded during scheduling time. Evan On Dec 10, 2009, at 11:46 AM, Javier Martinez wrote: > Hello, > > My expansion for an operation uses if and loops. How do I introduce > branches in the target

Hi, all, I have been recently porting a backend for our experimental DSP. It has a regular register file for ALU, naming it R registers, and another register file (J registers) for memory access. Both R registers and J registers are 32-bit. Since LLVM cannot distinguish 32-bit integers or pointers during register allocation, I have to define J as 64-bit, although it's physically 32-bit. This

Hello > I'm trying to understand how fitting source integer type width into > target machine register width happens. My reading on LLVM > codegeneration topics (few megabytes) so far didn't have this topic > mentioned explicitly. This is done during DAG Legalization phase. The operation is splitted into two (ADD + ADDC / ADDE). These DAG nodes are later matches during

Hello, My expansion for an operation uses if and loops. How do I introduce branches in the target lowering stage? Do I have to create basic blocks, add the instructions to them and and add them to the machine function's basic block list? Thanks, Javier

Hello, I'm trying to understand how fitting source integer type width into target machine register width happens. My reading on LLVM codegeneration topics (few megabytes) so far didn't have this topic mentioned explicitly. As an example, how %1 = add nsw i32 %b, %a gets compiled into msp430 (16bit CPU) assembly as: add.w r13, r15 addc.w r12, r14 Using -print-before-all