search for: expandintegerresult

I tried to build VMKit on an ARM device today (a Sheevaplug - armv5te) (native, not cross compiled), and got this error: llvm[3]: Building LLVM assembly with /home/debio/build/vmkit-build/vmkit/lib/Mvm/Runtime/LLVMAssembly.ll /home/debio/build/vmkit-build/vmkit/lib/Mvm/Runtime/LLVMAssembly64.ll ExpandIntegerResult #0: 0x16fbf88: i64,ch = AtomicCmpSwap 0x16e8d84, 0x16fbf00, 0x16fc3c8, 0x16fc1a8<Volatile LDST8[%ptr]> [ORD=4] [ID=0] Do not know how to expand the result of this operator! UNREACHABLE executed at LegalizeIntegerTypes.cpp:982! Stack dump: 0. Program arguments: /home/debio/build/vmkit-bu...

...the return type (i64) is not legal, LLVM ends up calling into ReplaceNodeResults(). ReplaceNodeResults() has the restriction that the result has to have the same number of values and types. This forces the lowering function to return a target defined custom i64 node. At the next legalization cycle ExpandIntegerResults() is called to expand this node causing an assert because getOperationAction doesn't operate on custom nodes. Am I doing something wrong? My goal is to provide an expansion for 64-bit division that unfortunately uses branches for a target that doesn't support 64-bit integers. Thanks, Jav...

...DE). These DAG nodes are later matches during > instruction selection. Thanks for all the replies! Taking the hints, here's more datailed flow for the "%1 = add nsw i32 %b, %a" example if someone later will google for it: Source file is LegalizeIntegerTypes.cpp, DAGTypeLegalizer::ExpandIntegerResult(SDNode *N, unsigned ResNo). handles width splitting (which apparently in LLVM slang called "expanding" which I'm, as a novice, find confusing). For add/sub, this calls DAGTypeLegalizer::ExpandIntRes_ADDSUB(SDNode *N, SDValue &Lo, SDValue &Hi) which splits value operation int...

...addr = alloca i32, align 4 store i32 %i, i32* %i.addr, align 4 store i32 %j, i32* %j.addr, align 4 %0 = load i32* %i.addr, align 4 %1 = load i32* %j.addr, align 4 %cmp = icmp sgt i32 %0, %1 %cond = select i1 %cmp, i32 1, i32 0 ret i32 %cond } (3) llc -march=sparcv9 test.ll -o test.s ExpandIntegerResult #0: 0xaf38960: i64 = FrameIndex<1> [ORD=2] [ID=0] Do not know how to expand the result of this operator! UNREACHABLE executed at /home/yangyy/git.repo/llvm.git/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp:1089! 0 llc 0x08c2512b Stack dump: 0. Program arguments: llc -march=sparcv9 test....

..., I'm trying to use llvm/clang to cross compile to sparcv9. The following works with a -march=sparc, but yields errors for sparcv9. Are there some other flags that need to be specified? Thanks, Tarun > clang -m64 -emit-llvm test.c -c -o test.bc > llc -march=sparcv9 test.bc -o hello.s ExpandIntegerResult #0: 0x8a6c478: i64 = GlobalAddress<[4 x i8]* @.str> 0 [ORD=1] [ID=0] Do not know how to expand the result of this operator! UNREACHABLE executed at ~/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp:947! 0 libLLVM-2.8svn.so 0xf6f82ef8 1 libLLVM-2.8svn.so 0xf6f82d90 2...

...[ORD=161] [ID=0] Promote integer operand: 0x56059c0: f32 = fpowi 0x5602580, 0x56061c0 [ORD=162] [ID=0] PromoteIntegerOperand Op #1: 0x56059c0: f32 = fpowi 0x5602580, 0x56061c0 [ORD=162] [ID=0] Do not know how to promote this operator's operand! ------ This is coming out of DAGTypeLegalizer::ExpandIntegerResult(). I've tried adding some code to expand the integer operand (operand 1) via SIGN_EXTEND[_INREG] but keep getting other consistency errors. Another approach I tried was to set the calling convention: setLibcallCallingConv(RTLIB::POWI_F32, CallingConv::C); Which would seem to force the call to...

...dr, align 4 > store i32 %j, i32* %j.addr, align 4 > %0 = load i32* %i.addr, align 4 > %1 = load i32* %j.addr, align 4 > %cmp = icmp sgt i32 %0, %1 > %cond = select i1 %cmp, i32 1, i32 0 > ret i32 %cond > } > > (3) llc -march=sparcv9 test.ll -o test.s > > ExpandIntegerResult #0: 0xaf38960: i64 = FrameIndex<1> [ORD=2] [ID=0] > > Do not know how to expand the result of this operator! > UNREACHABLE executed at > /home/yangyy/git.repo/llvm.git/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp:1089! > 0 llc 0x08c2512b > Stack dump: > 0. Prog...

Hi, When expanding multiply operation in LegalizeTypes LLVM generates some nodes such as UMUL_LOHI (please refer file LegalizeIntegerTypes.cpp - function - ExpandIntegerResult). However while lowering this operation in LegalizeDAG (please refer file LegalizeDAG.cpp - function - LegalizeOp) the comment says "These nodes will only be produced by target-specific lowering.....". LLVM, therefore, does not call the LowerOperation for these operations. Fun...

See X86InstrInfo.td let usesCustomInserter = 1, isTwoAddress = 0, Defs = [EFLAGS] in def CMOV_GR8 : I<0, Pseudo, This creates a CMOV_GR8 pseudo instruction at isel time which can be expanded during scheduling time. Evan On Dec 10, 2009, at 11:46 AM, Javier Martinez wrote: > Hello, > > My expansion for an operation uses if and loops. How do I introduce > branches in the target

...I define my TargetData as "e-p:64:64:64-i32:32:32-f32:32:32-n32". When storing a register to stack frame, 'store' node take a FrameIndex as an input node, where FrameIndex produces a 64-bit operand for 'store'. In legalization phase, llc comes into a problem saying: ExpandIntegerResult #0: 0xadb1888: i64 = FrameIndex<1> [ORD=2] [ID=0] Do not know how to expand the result of this operator! To sovle this problem, I tried "-march=sparcv9" (LLVM 3.1 release version), the same problem occured. sparcv9 is a 64-bit target so FrameIndex operator produces i64 data,...

Hello > I'm trying to understand how fitting source integer type width into > target machine register width happens. My reading on LLVM > codegeneration topics (few megabytes) so far didn't have this topic > mentioned explicitly. This is done during DAG Legalization phase. The operation is splitted into two (ADD + ADDC / ADDE). These DAG nodes are later matches during

Hello, My expansion for an operation uses if and loops. How do I introduce branches in the target lowering stage? Do I have to create basic blocks, add the instructions to them and and add them to the machine function's basic block list? Thanks, Javier

Hello, I'm trying to understand how fitting source integer type width into target machine register width happens. My reading on LLVM codegeneration topics (few megabytes) so far didn't have this topic mentioned explicitly. As an example, how %1 = add nsw i32 %b, %a gets compiled into msp430 (16bit CPU) assembly as: add.w r13, r15 addc.w r12, r14 Using -print-before-all