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On Thu, Mar 17, 2016 at 2:41 PM, Rail Shafigulin <rail at esenciatech.com> wrote: > On Thu, Mar 17, 2016 at 10:10 AM, Rail Shafigulin <rail at esenciatech.com> > wrote: > >> On Wed, Mar 16, 2016 at 6:38 PM, Mehdi Amini <mehdi.amini at apple.com> >> wrote: >> >>> >>> On Mar 16, 2016, at 5:38 PM, Rail Shafigu...

> On Mar 18, 2016, at 12:52 PM, Mehdi Amini <mehdi.amini at apple.com> wrote: > >> >> On Mar 18, 2016, at 12:45 PM, Rail Shafigulin <rail at esenciatech.com <mailto:rail at esenciatech.com>> wrote: >> >> On Thu, Mar 17, 2016 at 2:41 PM, Rail Shafigulin <rail at esenciatech.com <mailto:rail at esenciatech.com>> wrote: >> On Thu, Mar 17, 2016 at 10:10 AM, Rail Shafigulin <rail at esenciatech.com <mailto:r...

On Fri, Mar 18, 2016 at 2:03 PM, Rail Shafigulin <rail at esenciatech.com> wrote: > On Fri, Mar 18, 2016 at 1:53 PM, Mehdi Amini <mehdi.amini at apple.com> > wrote: > >> >> On Mar 18, 2016, at 1:47 PM, Rail Shafigulin <rail at esenciatech.com> >> wrote: >> >> Yes this IR does not build or shuffle any vector. Try...

On Wed, Mar 16, 2016 at 6:38 PM, Mehdi Amini <mehdi.amini at apple.com> wrote: > > On Mar 16, 2016, at 5:38 PM, Rail Shafigulin <rail at esenciatech.com> wrote: > > On Wed, Mar 16, 2016 at 11:48 AM, Mehdi Amini <mehdi.amini at apple.com> > wrote: > >> Hi Rail, >> >> Two hints to begin with: >> >> 1) Makes sure you example is vectorized on X86 for example >> 2) Is your target correctly ove...

...for each of the permutations, but it is verbose, and in practice most people only write it one way anyway. The 8-lane equivalent has TableGen left thinking for quite a long time, and the 16-lane equivalent seems to hang TableGen. MartinO From: Rail Shafigulin [mailto:rail at esenciatech.com] Sent: 16 May 2016 23:50 To: Martin J. O'Riordan Cc: LLVM Developers Subject: Re: [llvm-dev] sum elements in the vector On Mon, May 16, 2016 at 3:11 AM, Martin J. O'Riordan via llvm-dev <llvm-dev at lists.llvm.org <mailto:llvm-dev at lists.llvm.org> > wrote: This...

> On Mar 18, 2016, at 1:47 PM, Rail Shafigulin <rail at esenciatech.com> wrote: > > Yes this IR does not build or shuffle any vector. Try to write a function that takes 8 ints and a pointer to a <4xi32>, builds two vectors with the 8 ints, > > This might sound like a dumb question, but how does one build a vector of ints out of regular ints i...

On Tue, Feb 2, 2016 at 8:42 PM, Matt Arsenault <arsenm2 at gmail.com> wrote: > > On Feb 2, 2016, at 16:52, Rail Shafigulin <rail at esenciatech.com> wrote: > > def SDT_EscalaSetFlag : SDTypeProfile<0, 3, [SDTCisSameAs<0, 1>]>; > > > I think for setting an implicit register, you still need to have 1 result > here. > > If you look at SDTX86CmpPTest, I think this is similar to what you are > tryi...

...represent “sum of elements in a vector” and generate your particular instruction.However, you can do it without intrinsic by pattern matching the LLVM-IRs representing “sum of elements in vector” to your particular instruction in DAGCombiner. Regards, Shahid From: Rail Shafigulin [mailto:rail at esenciatech.com] Sent: Monday, May 09, 2016 11:59 PM To: Shahid, Asghar-ahmad; llvm-dev Cc: Das, Dibyendu Subject: Re: [llvm-dev] sum elements in the vector I'm a little confused. Here is why. I was able to add a vector add instruction to my target without using any intrinsics and without adding any new...

On Tue, Feb 2, 2016 at 1:41 AM, Rail Shafigulin <rail at esenciatech.com> wrote: > > Let me clarify. >> >> I'm not sure I understand what you are saying. Let me post more >> information. >> >> Here is what I have defined for Escalasetflag >> >> def Escalasetflag : SDNode<"EscalaISD::SET_FLAG",...

...sum of elements in a vector” and generate your particular instruction.However, you can do it without intrinsic by pattern matching the LLVM-IRs representing “sum of elements in vector” to your particular instruction in DAGCombiner. Regards, Shahid From: Rail Shafigulin [mailto:rail at esenciatech.com <mailto:rail at esenciatech.com> ] Sent: Monday, May 09, 2016 11:59 PM To: Shahid, Asghar-ahmad; llvm-dev Cc: Das, Dibyendu Subject: Re: [llvm-dev] sum elements in the vector I'm a little confused. Here is why. I was able to add a vector add instruction to my target without...

...n.However, you can do it without > intrinsic by pattern matching the > > LLVM-IRs representing “sum of elements in vector” to your particular > instruction in DAGCombiner. > > > > Regards, > > Shahid > > > > > > *From:* Rail Shafigulin [mailto:rail at esenciatech.com] > *Sent:* Monday, May 09, 2016 11:59 PM > *To:* Shahid, Asghar-ahmad; llvm-dev > *Cc:* Das, Dibyendu > > > *Subject:* Re: [llvm-dev] sum elements in the vector > > > > I'm a little confused. Here is why. > > > > I was able to add a vector add instr...

> > No, this would have to be a void side effecting instruction which is a bit > different. What do you mean by "void side effecting instruction"? I'm not sure I fully understand what you mean. The flag register is an implicit register added to the selected > MachineInstr's operands. Is this something that is always done by LLVM? Is it me who is telling to LLVM

...rget this new instruction (sum elements in a vector) if it is implemented as an intrinsic or the user will have to specifically invoke an instrinsic. Pardon if questions seem dumb, I'm still learning things. Any help is appreciated. On Fri, May 6, 2016 at 1:51 PM, Rail Shafigulin <rail at esenciatech.com> wrote: > Thanks for the reply. These steps will add an instruction as an intrinsic. > Is it possible to add an actual new instruction so that a compiler could > target it during an optimization? How hard is it to do it? Is that a > realistic objective. > > Rail > >...

...a / --------- add / \ / b DEF \ c \ / ---------- sub \ d And so on and so fourth. ​ On Sat, Jan 30, 2016 at 8:54 AM, Rail Shafigulin <rail at esenciatech.com> wrote: > > > On Fri, Jan 29, 2016 at 11:39 AM, Rail Shafigulin <rail at esenciatech.com> > wrote: > >> >> >> On Thu, Jan 28, 2016 at 8:34 PM, Dylan McKay <dylanmckay34 at gmail.com> >> wrote: >> >>> Try visualising the DAG l...

> > Here is how I started with SelectionDAG: > > - small IR (bugpoint can help) > Did you mean a break poing? - the magic flag: -debug > - read the output of SelectionDAG debugging (especially with cycles) > - matching the log to source code > What log are you talking about? > - single stepping in a debugger sometimes. > > > -- > Mehdi > > -- Rail

> > -Most- targets use -march. > > -eric > Do you meat that in most cases -target is used along with -march instead of -target and -mcpu? -- Rail Shafigulin Software Engineer Esencia Technologies -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20160318/9efe3d1b/attachment.html>

...odify the scheduler to do so (optionally) or it would be too complicated. If possible, what would be the right place to look ? Thanks so much Miguel On Tue, Aug 16, 2011 at 3:54 PM, Eli Friedman <eli.friedman at gmail.com>wrote: > On Mon, Aug 15, 2011 at 4:03 PM, Miguel G <miguel at esenciatech.com> wrote: > > Hi everyone > > I'm fairly new with LLVM and I've been searching around but couldn't find > > info on this subject. > > I started working on a target for a new cpu and I realizing my initial > > simple understanding of instruction itinera...

On Fri, Jan 29, 2016 at 11:39 AM, Rail Shafigulin <rail at esenciatech.com> wrote: > > > On Thu, Jan 28, 2016 at 8:34 PM, Dylan McKay <dylanmckay34 at gmail.com> > wrote: > >> Try visualising the DAG like this. >> >> ``` >> ---- GPR:$rA >> / >> set GPR:$rd ---- a...

On Thu, Jan 28, 2016 at 8:34 PM, Dylan McKay <dylanmckay34 at gmail.com> wrote: > Try visualising the DAG like this. > > ``` > ---- GPR:$rA > / > set GPR:$rd ---- add > \ > ---- GPR:$rB > ``` > > Each instruction forms a DAG with its operands being subnodes. > >

Is there a way to convert between SchedMachineModel and Itineraries? I was trying to write a very simple VLIW packetizer (Hexagon was my starting point). It turns out that current DFAPacketizer is using itineraries, but my schedule is based on SchedMachineModel (I was recommended to use it since the itineraries are being phased out). I was wondering if there is an automated tool that would