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> On Nov 13, 2018, at 08:01, David Greene <dag at cray.com> wrote: > > Daniel Sanders via llvm-dev <llvm-dev at lists.llvm.org> writes: > >> That's an interesting idea. Certainly tablegenerating InstCombine >> ought to be possible and sharing code sounds like it ought to be >> doable. MIR and IR are pretty similar especially after IRTranslator >> (which is a direct translation) through to the Legalizer (which is the >> first point target instructions can until ta...

...0s remaining] / Done encoding file "track03.cdda.ogg" File length: 5m 01.0s Elapsed time: 1m 26.9s Rate: 3.4704 Average bitrate: 133.3 kb/s But when I try to play the resulting file, I get silence. When I try it in XMMS, the seek bar jumps eratically, as does the track time and the bit rate. I have tried this with the default bit rate, and with 256. The wav file is straight from cdparanoia - it works fine with Lame. Any advice you can give to get this working would be great... I've added Ogg Vorbis support to T.E.A.R (CD ripper/enc...

...to me. Specific comments are below. > > But before that, I've been long pained that we have so much duplicated > code in instcombine and dagcombine. I know this is way beyond the scope > of this work but do you think the basic concepts could be applied to > produce TableGen-generated instcombine passes? It would be nice to > re-use many of the rules, for example, except they'd match LLVM IR > rather than MIR. As you go about implementation, maybe keep this idea > in mind? > > > Here's a simple example that eliminates a redundant G_TRUNC. > >...

Le mer. 28 nov. 2018 à 11:41, David Greene <dag at cray.com> a écrit : > > Quentin Colombet <quentin.colombet at gmail.com> writes: > > > And are there any realistic alternatives for declarative > > representations combines? > > > > Realistic I would have thought we can use the syntax we already have > > for SDISel. > > In other

...tters (see my comments below) and I am afraid we still don't know all that needs to be represented. > It can reach across basic blocks when it's safe to do so. We may need to introduce a means to limit the inter-basic-block reach as I can foresee situations where it may pull expensive operations into a loop if it's not careful about this I think we would need a syntax for that and in particular, I don't think a generic heuristic based on frequency can solely solve the problem (i.e., what you're hinting in your RFC). Another thing that we miss has to do with the number of...

Hi Nicolai, Le ven. 9 nov. 2018 à 09:24, Nicolai Hähnle <nhaehnle at gmail.com> a écrit : > > Hi Quentin, > > On 09.11.18 18:16, Quentin Colombet via llvm-dev wrote: > > Disclaimer: Haven't read the proposal yet. > > > >> TL;DR: We're planning to define GlobalISel Combine Rules using MIR syntax with a few bits glued on to interface with the

...nts below) and I am afraid we still don't know all that > needs to be represented. > > It can reach across basic blocks when it's safe to do so. We may need to > introduce a means to limit the inter-basic-block reach as I can foresee > situations where it may pull expensive operations into a loop if it's not > careful about this > > > I think we would need a syntax for that and in particular, I don't > think a generic heuristic based on frequency can solely solve the > problem (i.e., what you're hinting in your RFC). > > > That's so...

...to me. Specific comments are below. > > But before that, I've been long pained that we have so much duplicated > code in instcombine and dagcombine. I know this is way beyond the scope > of this work but do you think the basic concepts could be applied to > produce TableGen-generated instcombine passes? It would be nice to > re-use many of the rules, for example, except they'd match LLVM IR > rather than MIR. As you go about implementation, maybe keep this idea > in mind? That's an interesting idea. Certainly tablegenerating InstCombine ought to be possibl...

...11) Unknown type '&'_info:Tt(0,29)=s36eh_info:(7,38),0,64;value:(0,20),64,32;type:(0,20),96,32;cleanup:(0,26),128,32;caught:(0,12),160,8failure on __throw_bad_typeid:F(0,37)=&(0,38)=xstype_info: at (0,38)=xstype_info:erator=::(0,31)=##(0,32)=&(0,29);:__as__10cp_e failure on __ti9type_info:G(0,66)=ar(12,3);0;7;(0,11) at ;0;7;(0,11) Nothing has been defined <;0;11;(0,11)>...

Hi, I installed this program but I am not able to configure, it does not want to work. Someone can help me?

...failure on __vt_17__class_type_info:G(0,32)=ar(12,3);0;6;(0,23) at ;0;6;(0,23) Nothing has been defined <;0;4;(0,23)>8!1,020,(3,1);nonvirtual_base_type:/2(2,3):_16__user_type_info.nonvirtual_base_type;operator=:failure on __vt_10bad_typeid:G(0,64)=ar(12,3);0;4;(0,23) at ;0;4;(0,23)2A.;__user_type_info::(0,54)=##(0,55)=*(2,19);:RC16__use failure on bl:p(0,26)=*(2,17) at Nothing has been defined <;0...

I just realised I hadn't updated the version of PHP Markdown and Extra on the dingus as I pretended I did in my two announcements. It is now fixed: PHP Markdown 1.0.2b7 and PHP Markdown Extra 1.1b1 can now be tested on the dingus. <http://www.michelf.com/projects/php-markdown/dingus/> Sorry for any inconvenience. Michel Fortin michel.fortin@michelf.com http://www.michelf.com/

Hi Sean, Just to give the GlobalISel perspective on this, GlobalISel supports the declaration of a zero register in the register class like so: def GPR32z : RegisterOperand<GPR32> { let GIZeroRegister = WZR; } With that definition, the tablegen-erated ISel code will try to replace will try to replace 'G_CONSTANT s32 0' with WZR whenever the operand is specified as GPR32z. > On 21 Dec 2017, at 21:22, Sean Silva via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > I looked around the codebase and didn't see anything...

...el perspective on this, Thanks for chiming in! > GlobalISel supports the declaration of a zero register in the register > class like so: > def GPR32z : RegisterOperand<GPR32> { > let GIZeroRegister = WZR; > } > With that definition, the tablegen-erated ISel code will try to replace > will try to replace 'G_CONSTANT s32 0' with WZR whenever the operand is > specified as GPR32z. > Is this method extensible to the case of other hardwired register values? Tracing through the code, I noticed that it seems to boil down to a GIR_Cop...

...ants the installed driver > > package from system32 directory > > > > With all drivers I get the message > > > > "Add Printer Driver Wizard > > Unable to install Kyocera ECOSYS P6230cdn KX (XPS), Type 3 - > > User Mode, x64 driver. > > This operation is not supported." > > > > after files have been copied to the print$ share into > > x64/{...} or W32X86/{...} directories. I can't find anything > > enlightening in the samba log files (low log level shows > > nothing helpful, high log level shows to m...

...un a database application using shared table and index files on a Samba 2.2.2 server (Suse Linux 7.2). The application was just ported from Clipper to XBase++. The Clipper compiled app (it's a 16-bit DOS application) runs fine. The 32-bit XBase++ app produces corrupt index files and behaves eratically after several minutes under normal workload. Of course I was blaming the XBase++ compiler first. I then tried playing around with the locking settings in smb.conf, trying to set Samba to what I thought would be the least aggressive configuration (oplock OFF, blocking locks OFF, strict loc...

...; package from system32 directory > > > > > > With all drivers I get the message > > > > > > "Add Printer Driver Wizard > > > Unable to install Kyocera ECOSYS P6230cdn KX (XPS), Type 3 - > > > User Mode, x64 driver. > > > This operation is not supported." > > > > > > after files have been copied to the print$ share into > > > x64/{...} or W32X86/{...} directories. I can't find anything > > > enlightening in the samba log files (low log level shows > > > nothing helpful,...

...tput file. There are however, some simple rules we can use to minimize the defs section with just a scan of the defs section (trivial) and match section (which we have to do anyway): Match roots are implicitly declared in the defs section and have type 'reg'. Names used as argument to an operator that subclasses Instruction are implicitly declared in the defs section with type 'reg'. This allows leaf-operands to be used in the apply section This does however come at additional run-time memory cost Names used as argument to an operator that subclasses Instruction are assumed to be...

...) and I am afraid we still don't know all that > > needs to be represented. > > > >> It can reach across basic blocks when it's safe to do so. We may need to introduce a means to limit the inter-basic-block reach as I can foresee situations where it may pull expensive operations into a loop if it's not careful about this > > > > I think we would need a syntax for that and in particular, I don't > > think a generic heuristic based on frequency can solely solve the > > problem (i.e., what you're hinting in your RFC). > > That'...