Displaying 6 results from an estimated 6 matches for "entryvecti".
Did you mean:
entryvecty
2013 Nov 12
2
[LLVMdev] Implementing the ldr pseudo instruction in ARM integrated assembler
Hi David,
Thanks for your efforts here. I have a few comments on your patch, although
I realise it's still a work in progress.
+class ConstantPool {
+ MCSymbol *Label;
+ typedef std::vector<const MCExpr*> EntryVecTy;
Use a SmallVector here?
+ MCSymbol *getLabel() {return Label;}
+ size_t getNumEntries() {return Entries.size();}
+ const MCExpr *getEntry(size_t Num) {return
2013 Nov 12
0
[LLVMdev] Implementing the ldr pseudo instruction in ARM integrated assembler
Hi Amara,
Thanks for your suggestions. I have made the changes you suggested and added
a new test to check that we print an error when parsing a non-ldr mnemonic
with an operand containing `=`. The updated patch is attached.
-- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted
by The Linux Foundation
> -----Original Message-----
> From: Amara Emerson
2013 Nov 16
2
[LLVMdev] Implementing the ldr pseudo instruction in ARM integrated assembler
Moving discussion to llvm-commits now that I have a more developed
implementation:
http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20131111/195401.
html
> -----Original Message-----
> From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] On
> Behalf Of David Peixotto
> Sent: Tuesday, November 12, 2013 11:09 AM
> To: 'Amara Emerson'
>
2013 Nov 11
0
[LLVMdev] Implementing the ldr pseudo instruction in ARM integrated assembler
I have attached an initial patch that implements the ldr pseudo. It still
needs some clean up and more tests, but I would like some feedback on the
approach I used and if there are any objections to implementing it this way.
Here is my approach:
Add a finishParse() callback to the target asm parser
This callback is invoked when the parse has finished
successfully. It will be used to write out
2013 Dec 17
0
[LLVMdev] Implementing the ldr pseudo instruction in ARM integrated assembler
Hi David,
Maybe I’m just blind, but where’s the code to handle the .ltorg directive? Is that a separate patch, maybe? Without that, this is not going to be usable in any circumstance using subsections-via-symbols.
+typedef std::map<const MCSection *, ConstantPool> ConstantPoolMapTy;
This feels odd to me. Can you elaborate a bit more on the data structure choices?? I would have expected
2013 Nov 01
8
[LLVMdev] Implementing the ldr pseudo instruction in ARM integrated assembler
In an earlier email[1] I proposed adding support for the ldr
pseud-instruction to the ARM integrated assembler. After some discussion the
overall consensus seemed to be that it was worth adding. One concern was
that we needed to have adequate testing. I promised to provide more details
on what the behavior should be and provide some tests before starting the
implementation. The FileCheck-ified