search for: end23

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[LLVMdev] introducing sign extending halfword loads into the LLVM IR
2013 Jan 21
2
[LLVMdev] introducing sign extending halfword loads into the LLVM IR
...arison on the non-extended value; the result is a comparison operation on 16-bit operands, followed by a select operation on 32-bit operands: %0 = load i16* %arrayidx2, align 2, !dbg !502 %conv = sext i16 %0 to i32, !dbg !502 %cmp16 = icmp sgt i16 %0, 2047, !dbg !510 br i1 %cmp16, label %if.end23, label %if.else, !dbg !510 if.else: ; preds = %for.body %cmp19 = icmp slt i16 %0, -2048, !dbg !511 <--- 16-bit comparison %.conv = select i1 %cmp19, i32 -2048, i32 %conv, !dbg !511 <--- 32-bit select...
[LLVMdev] introducing sign extending halfword loads into the LLVM IR
2013 Jan 21
0
[LLVMdev] introducing sign extending halfword loads into the LLVM IR
...lue; the result is a comparison operation on 16-bit > operands, followed by a select operation on 32-bit operands: > > %0 = load i16* %arrayidx2, align 2, !dbg !502 > %conv = sext i16 %0 to i32, !dbg !502 > %cmp16 = icmp sgt i16 %0, 2047, !dbg !510 > br i1 %cmp16, label %if.end23, label %if.else, !dbg !510 > > if.else: ; preds = %for.body > %cmp19 = icmp slt i16 %0, -2048, !dbg !511 > <--- 16-bit comparison > %.conv = select i1 %cmp19, i32 -2048, i32 %conv, !dbg !511 <--- > 32-bit select...
[LLVMdev] introducing sign extending halfword loads into the LLVM IR
2013 Jan 21
2
[LLVMdev] introducing sign extending halfword loads into the LLVM IR
...d value; the result is a comparison operation on 16-bit operands, followed by a select operation on 32-bit operands: > > %0 = load i16* %arrayidx2, align 2, !dbg !502 > %conv = sext i16 %0 to i32, !dbg !502 > %cmp16 = icmp sgt i16 %0, 2047, !dbg !510 > br i1 %cmp16, label %if.end23, label %if.else, !dbg !510 > > if.else: ; preds = %for.body > %cmp19 = icmp slt i16 %0, -2048, !dbg !511 <--- 16-bit comparison > %.conv = select i1 %cmp19, i32 -2048, i32 %conv, !dbg !511 &...
[LLVMdev] introducing sign extending halfword loads into the LLVM IR
2013 Jan 21
3
[LLVMdev] introducing sign extending halfword loads into the LLVM IR
...is a comparison operation on 16-bit operands, followed by a select operation on 32-bit operands: >> >> %0 = load i16* %arrayidx2, align 2, !dbg !502 >> %conv = sext i16 %0 to i32, !dbg !502 >> %cmp16 = icmp sgt i16 %0, 2047, !dbg !510 >> br i1 %cmp16, label %if.end23, label %if.else, !dbg !510 >> >> if.else: ; preds = %for.body >> %cmp19 = icmp slt i16 %0, -2048, !dbg !511 <--- 16-bit comparison >> %.conv = select i1 %cmp19, i32 -2048, i32 %conv, !dbg...
[LLVMdev] introducing sign extending halfword loads into the LLVM IR
2013 Jan 21
0
[LLVMdev] introducing sign extending halfword loads into the LLVM IR
...parison operation on 16-bit >> operands, followed by a select operation on 32-bit operands: >> >> %0 = load i16* %arrayidx2, align 2, !dbg !502 >> %conv = sext i16 %0 to i32, !dbg !502 >> %cmp16 = icmp sgt i16 %0, 2047, !dbg !510 >> br i1 %cmp16, label %if.end23, label %if.else, !dbg !510 >> >> if.else: ; preds = %for.body >> %cmp19 = icmp slt i16 %0, -2048, !dbg !511 >> <--- 16-bit comparison >> %.conv = select i1 %cmp19, i32 -2048, i32 %conv, !dbg !511 >> <...