Displaying 14 results from an estimated 14 matches for "efer_nx".
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_efer_nx
2010 Aug 05
3
[PATCH 08/14] Nested Virtualization: efer
Signed-off-by: Christoph Egger <Christoph.Egger@amd.com>
--
---to satisfy European Law for business letters:
Advanced Micro Devices GmbH
Einsteinring 24, 85609 Dornach b. Muenchen
Geschaeftsfuehrer: Alberto Bozzo, Andrew Bowd
Sitz: Dornach, Gemeinde Aschheim, Landkreis Muenchen
Registergericht Muenchen, HRB Nr. 43632
_______________________________________________
Xen-devel mailing list
2010 May 04
0
[PATCH] svm: support EFER.LMSLE for guests
...vm.c 2010-04-22 14:43:25.000000000 +0200
+++ 2010-05-04/xen/arch/x86/hvm/hvm.c 2010-05-04 13:26:07.000000000 +0200
@@ -590,6 +590,7 @@ static bool_t hvm_efer_valid(uint64_t va
((sizeof(long) != 8) && (value & EFER_LME)) ||
(!cpu_has_nx && (value & EFER_NX)) ||
(!cpu_has_syscall && (value & EFER_SCE)) ||
+ (!cpu_has_lmsl && (value & EFER_LMSLE)) ||
(!cpu_has_ffxsr && (value & EFER_FFXSE)) ||
((value & (EFER_LME|EFER_LMA)) == EFER_LMA));
}
@@ -641,7 +642,8 @...
2005 Jul 13
2
RE: Re: [Xen-changelog] Fix NX/XD enable on secondary CPUs.
Whether the processor is in 32 or 64-bit mode, if NX is used, then
EFER_NX needs to be set. If NX isn''t used, then it''s a "Don''t care". I
think bad things happens if you set the NX bit in the page table and
don''t have EFER_NX set...
--
Mats
> -----Original Message-----
> From: xen-devel-bounces@lists.xensource.com
&g...
2007 Aug 09
1
[PATCH] svm: allow guest to use EFER.FFXSE and EFER.LMSLE
...ned char cpu_has_lmsl = 1;
+#endif
+
/* SVM feature flags */
u32 svm_feature_flags;
@@ -190,7 +195,10 @@ static enum handler_return long_mode_do_
case MSR_EFER:
/* Offending reserved bit will cause #GP. */
#ifdef __x86_64__
- if ( (msr_content & ~(EFER_LME | EFER_LMA | EFER_NX | EFER_SCE)) ||
+ if ( (msr_content & ~(EFER_FFXSE | EFER_LMSLE | EFER_LME | EFER_LMA |
+ EFER_NX | EFER_SCE)) ||
+ (!cpu_has_lmsl && (msr_content & EFER_LMSLE)) ||
+ (!cpu_has_ffxsr && (msr_content & EFER_FFXSE...
2005 Jul 13
2
Re: [Xen-changelog] Fix NX/XD enable on secondary CPUs.
Xen patchbot -unstable <patchbot-unstable@lists.xensource.com> writes:
> Fix NX/XD enable on secondary CPUs.
> Signed-off-by: Keir Fraser <keir@xensource.com>
I think I have this problem with PAE as well. Machine is SMP
(hyperthreaded). PAE dom0 boots fine on CPU #0. PAE domU is bound to
CPU #1 by default and boots to the login prompt as well, but only with
NX disabled (and
2007 Jan 31
7
[PATCH][SVM] remove FFXSR CPUID bit for AMD-V HVM guests
Remove visibility of the FFXSR CPUID bit to an HVM guest.
This patch allows HVM Windows x64 to install/boot on AMD-V platforms.
This patches applies cleanly to xen-unstable 13743.
Please apply to xen-unstable/3.0.5.
If possible, pls apply to xen-3.0.4-testing.
--Tom
thomas.woller@amd.com
AMD Corporation
5204 E. Ben White Blvd. UBC1
Austin, Texas 78741
+1-512-602-0059
2007 Apr 18
1
No subject
...ASE 0xc0000101 /* 64bit GS base */
+#define MSR_KERNEL_GS_BASE 0xc0000102 /* SwapGS GS shadow */
+
+/* EFER bits: */
+#define _EFER_SCE 0x00000000 /* SYSCALL/SYSRET */
+#define _EFER_LME 0x00000008 /* Long mode enable */
+#define _EFER_LMA 0x0000000a /* Long mode active (read-only) */
+#define _EFER_NX 0x0000000b /* No execute enable */
+
+#define EFER_SCE (1<<_EFER_SCE)
+#define EFER_LME (1<<_EFER_LME)
+#define EFER_LMA (1<<_EFER_LMA)
+#define EFER_NX (1<<_EFER_NX)
+
+/* Intel MSRs. Some also available on other CPUs */
+#define MSR_IA32_PERFCTR0 0x000000c1
+#define...
2007 Apr 18
1
No subject
...ASE 0xc0000101 /* 64bit GS base */
+#define MSR_KERNEL_GS_BASE 0xc0000102 /* SwapGS GS shadow */
+
+/* EFER bits: */
+#define _EFER_SCE 0x00000000 /* SYSCALL/SYSRET */
+#define _EFER_LME 0x00000008 /* Long mode enable */
+#define _EFER_LMA 0x0000000a /* Long mode active (read-only) */
+#define _EFER_NX 0x0000000b /* No execute enable */
+
+#define EFER_SCE (1<<_EFER_SCE)
+#define EFER_LME (1<<_EFER_LME)
+#define EFER_LMA (1<<_EFER_LMA)
+#define EFER_NX (1<<_EFER_NX)
+
+/* Intel MSRs. Some also available on other CPUs */
+#define MSR_IA32_PERFCTR0 0x000000c1
+#define...
2007 Apr 18
2
[PATCH] Clean up x86 control register and MSR macros (corrected)
...ASE 0xc0000101 /* 64bit GS base */
+#define MSR_KERNEL_GS_BASE 0xc0000102 /* SwapGS GS shadow */
+
+/* EFER bits: */
+#define _EFER_SCE 0x00000000 /* SYSCALL/SYSRET */
+#define _EFER_LME 0x00000008 /* Long mode enable */
+#define _EFER_LMA 0x0000000a /* Long mode active (read-only) */
+#define _EFER_NX 0x0000000b /* No execute enable */
+
+#define EFER_SCE (1<<_EFER_SCE)
+#define EFER_LME (1<<_EFER_LME)
+#define EFER_LMA (1<<_EFER_LMA)
+#define EFER_NX (1<<_EFER_NX)
+
+/* Intel MSRs. Some also available on other CPUs */
+#define MSR_IA32_PERFCTR0 0x000000c1
+#define...
2007 Apr 18
2
[PATCH] Clean up x86 control register and MSR macros (corrected)
...ASE 0xc0000101 /* 64bit GS base */
+#define MSR_KERNEL_GS_BASE 0xc0000102 /* SwapGS GS shadow */
+
+/* EFER bits: */
+#define _EFER_SCE 0x00000000 /* SYSCALL/SYSRET */
+#define _EFER_LME 0x00000008 /* Long mode enable */
+#define _EFER_LMA 0x0000000a /* Long mode active (read-only) */
+#define _EFER_NX 0x0000000b /* No execute enable */
+
+#define EFER_SCE (1<<_EFER_SCE)
+#define EFER_LME (1<<_EFER_LME)
+#define EFER_LMA (1<<_EFER_LMA)
+#define EFER_NX (1<<_EFER_NX)
+
+/* Intel MSRs. Some also available on other CPUs */
+#define MSR_IA32_PERFCTR0 0x000000c1
+#define...
2008 May 06
4
[PATCH] fixup 3dnow! support
...| 22 ++++++++++++++++++----
include/asm-x86/cpufeature.h | 2 ++
2 files changed, 20 insertions(+), 4 deletions(-)
diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
index 979f983..e79fcd5 100644
--- a/arch/x86/kvm/x86.c
+++ b/arch/x86/kvm/x86.c
@@ -919,7 +919,7 @@ static int is_efer_nx(void)
return efer & EFER_NX;
}
-static void cpuid_fix_nx_cap(struct kvm_vcpu *vcpu)
+static void cpuid_fix_caps(struct kvm_vcpu *vcpu)
{
int i;
struct kvm_cpuid_entry2 *e, *entry;
@@ -932,6 +932,20 @@ static void cpuid_fix_nx_cap(struct kvm_vcpu *vcpu)
break;
}
}
+
+ /* 3DNOW...
2008 May 06
4
[PATCH] fixup 3dnow! support
...| 22 ++++++++++++++++++----
include/asm-x86/cpufeature.h | 2 ++
2 files changed, 20 insertions(+), 4 deletions(-)
diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
index 979f983..e79fcd5 100644
--- a/arch/x86/kvm/x86.c
+++ b/arch/x86/kvm/x86.c
@@ -919,7 +919,7 @@ static int is_efer_nx(void)
return efer & EFER_NX;
}
-static void cpuid_fix_nx_cap(struct kvm_vcpu *vcpu)
+static void cpuid_fix_caps(struct kvm_vcpu *vcpu)
{
int i;
struct kvm_cpuid_entry2 *e, *entry;
@@ -932,6 +932,20 @@ static void cpuid_fix_nx_cap(struct kvm_vcpu *vcpu)
break;
}
}
+
+ /* 3DNOW...
2007 Apr 18
1
[RFC/PATCH LGUEST X86_64 03/13] lguest64 core
...MSR_GS_BASE:
+ val = (vcpu->guest_gs_a & ((1UL << 32)-1)) |
+ (vcpu->guest_gs_d << 32);
+ lhwrite_u64(vcpu, regs->rbx, val);
+ break;
+ case MSR_FS_BASE:
+ lhwrite_u64(vcpu, regs->rbx, 0);
+ break;
+ case MSR_EFER:
+ val = EFER_SCE | EFER_LME | EFER_LMA | EFER_NX;
+ lhwrite_u64(vcpu, regs->rbx, val);
+ break;
+ default:
+ kill_guest_dump(vcpu, "bad read of msr %llx\n", regs->rdx);
+ }
+ break;
+ case LHCALL_WRMSR:
+ switch (regs->rdx) {
+ case MSR_KERNEL_GS_BASE:
+ if ((regs->rbx >= HVVM_START) &&
+ (regs-&...
2007 Apr 18
1
[RFC/PATCH LGUEST X86_64 03/13] lguest64 core
...MSR_GS_BASE:
+ val = (vcpu->guest_gs_a & ((1UL << 32)-1)) |
+ (vcpu->guest_gs_d << 32);
+ lhwrite_u64(vcpu, regs->rbx, val);
+ break;
+ case MSR_FS_BASE:
+ lhwrite_u64(vcpu, regs->rbx, 0);
+ break;
+ case MSR_EFER:
+ val = EFER_SCE | EFER_LME | EFER_LMA | EFER_NX;
+ lhwrite_u64(vcpu, regs->rbx, val);
+ break;
+ default:
+ kill_guest_dump(vcpu, "bad read of msr %llx\n", regs->rdx);
+ }
+ break;
+ case LHCALL_WRMSR:
+ switch (regs->rdx) {
+ case MSR_KERNEL_GS_BASE:
+ if ((regs->rbx >= HVVM_START) &&
+ (regs-&...