Displaying 7 results from an estimated 7 matches for "_efer_nx".
2007 Apr 18
1
No subject
...BASE 0xc0000101 /* 64bit GS base */
+#define MSR_KERNEL_GS_BASE 0xc0000102 /* SwapGS GS shadow */
+
+/* EFER bits: */
+#define _EFER_SCE 0x00000000 /* SYSCALL/SYSRET */
+#define _EFER_LME 0x00000008 /* Long mode enable */
+#define _EFER_LMA 0x0000000a /* Long mode active (read-only) */
+#define _EFER_NX 0x0000000b /* No execute enable */
+
+#define EFER_SCE (1<<_EFER_SCE)
+#define EFER_LME (1<<_EFER_LME)
+#define EFER_LMA (1<<_EFER_LMA)
+#define EFER_NX (1<<_EFER_NX)
+
+/* Intel MSRs. Some also available on other CPUs */
+#define MSR_IA32_PERFCTR0 0x000000c1
+#define...
2007 Apr 18
1
No subject
...BASE 0xc0000101 /* 64bit GS base */
+#define MSR_KERNEL_GS_BASE 0xc0000102 /* SwapGS GS shadow */
+
+/* EFER bits: */
+#define _EFER_SCE 0x00000000 /* SYSCALL/SYSRET */
+#define _EFER_LME 0x00000008 /* Long mode enable */
+#define _EFER_LMA 0x0000000a /* Long mode active (read-only) */
+#define _EFER_NX 0x0000000b /* No execute enable */
+
+#define EFER_SCE (1<<_EFER_SCE)
+#define EFER_LME (1<<_EFER_LME)
+#define EFER_LMA (1<<_EFER_LMA)
+#define EFER_NX (1<<_EFER_NX)
+
+/* Intel MSRs. Some also available on other CPUs */
+#define MSR_IA32_PERFCTR0 0x000000c1
+#define...
2007 Apr 18
2
[PATCH] Clean up x86 control register and MSR macros (corrected)
...BASE 0xc0000101 /* 64bit GS base */
+#define MSR_KERNEL_GS_BASE 0xc0000102 /* SwapGS GS shadow */
+
+/* EFER bits: */
+#define _EFER_SCE 0x00000000 /* SYSCALL/SYSRET */
+#define _EFER_LME 0x00000008 /* Long mode enable */
+#define _EFER_LMA 0x0000000a /* Long mode active (read-only) */
+#define _EFER_NX 0x0000000b /* No execute enable */
+
+#define EFER_SCE (1<<_EFER_SCE)
+#define EFER_LME (1<<_EFER_LME)
+#define EFER_LMA (1<<_EFER_LMA)
+#define EFER_NX (1<<_EFER_NX)
+
+/* Intel MSRs. Some also available on other CPUs */
+#define MSR_IA32_PERFCTR0 0x000000c1
+#define...
2007 Apr 18
2
[PATCH] Clean up x86 control register and MSR macros (corrected)
...BASE 0xc0000101 /* 64bit GS base */
+#define MSR_KERNEL_GS_BASE 0xc0000102 /* SwapGS GS shadow */
+
+/* EFER bits: */
+#define _EFER_SCE 0x00000000 /* SYSCALL/SYSRET */
+#define _EFER_LME 0x00000008 /* Long mode enable */
+#define _EFER_LMA 0x0000000a /* Long mode active (read-only) */
+#define _EFER_NX 0x0000000b /* No execute enable */
+
+#define EFER_SCE (1<<_EFER_SCE)
+#define EFER_LME (1<<_EFER_LME)
+#define EFER_LMA (1<<_EFER_LMA)
+#define EFER_NX (1<<_EFER_NX)
+
+/* Intel MSRs. Some also available on other CPUs */
+#define MSR_IA32_PERFCTR0 0x000000c1
+#define...
2007 Aug 09
1
[PATCH] svm: allow guest to use EFER.FFXSE and EFER.LMSLE
...===========
--- 2007-08-08.orig/xen/include/asm-x86/msr.h 2007-08-07 15:00:27.000000000 +0200
+++ 2007-08-08/xen/include/asm-x86/msr.h 2007-08-08 11:43:53.000000000 +0200
@@ -140,12 +140,16 @@ static inline void wrmsrl(unsigned int m
#define _EFER_LMA 10 /* Long mode active (read-only) */
#define _EFER_NX 11 /* No execute enable */
#define _EFER_SVME 12
+#define _EFER_LMSLE 13
+#define _EFER_FFXSE 14
#define EFER_SCE (1<<_EFER_SCE)
#define EFER_LME (1<<_EFER_LME)
#define EFER_LMA (1<<_EFER_LMA)
#define EFER_NX (1<<_EFER_NX)
#define EFER_SVME (1<<_EFER_SVME)
+#d...
2007 Feb 14
4
[PATCH 3/12] Provide basic Xen PM infrastructure
...,2 @@ obj-y += boot.o
obj-y += boot.o
+obj-y += power.o
diff -r 13e258a58044 xen/arch/x86/boot/x86_32.S
--- a/xen/arch/x86/boot/x86_32.S Wed Feb 14 11:13:40 2007 +0800
+++ b/xen/arch/x86/boot/x86_32.S Wed Feb 14 11:13:40 2007 +0800
@@ -146,6 +146,8 @@ start_paging:
rdmsr
bts $_EFER_NX,%eax
wrmsr
+ mov $1,%eax
+ mov %eax, nx_enabled-__PAGE_OFFSET
no_execute_disable:
pop %ebx
#endif
diff -r 13e258a58044 xen/arch/x86/smp.c
--- a/xen/arch/x86/smp.c Wed Feb 14 11:13:40 2007 +0800
+++ b/xen/arch/x86/smp.c Wed Feb 14 14:59:49 2007 +0800
@@...
2007 Jun 27
0
[PATCH 1/10] Provide basic Xen PM infrastructure
....Lskip_eferw
+ movl $MSR_EFER,%ecx
+ rdmsr
+#if CONFIG_PAGING_LEVELS == 4
+ btsl $_EFER_LME,%eax /* Long Mode */
+ btsl $_EFER_SCE,%eax /* SYSCALL/SYSRET */
+#endif
+ btl $20,%edi /* No Execute? */
+ jnc 1f
+ btsl $_EFER_NX,%eax /* No Execute */
+1: wrmsr
+.Lskip_eferw:
+#endif
+
+ wbinvd
+
+ mov $0x80050033,%eax /* hi-to-lo: PG,AM,WP,NE,ET,MP,PE */
+ mov %eax,%cr0
+ jmp 1f
+1:
+
+#if defined(__x86_64__)
+
+ /* Now in compatibility mode. Long-jump to 64-bit mode...