Displaying 2 results from an estimated 2 matches for "ee1f21f5".
2017 Jun 28
0
Wide load/store optimization question
Well, that is now a slightly different question.
Once the compiler can do 64-bit loads/stores for a 64-bit integer type
(e.g. C long long), then an optimization pass should be merging the
loads/stores before register allocation, so that appropriate registers can
be chosen.
On Wed, Jun 28, 2017 at 5:43 AM, Peter Bel via llvm-dev <
llvm-dev at lists.llvm.org> wrote:
> Hi,
>
>
2017 Jun 28
2
Wide load/store optimization question
Hi,
I've looked through both AMDGPU and Sparc backends, and it seems they also
do not perform the thing I want to make. The only backend which is doing it
is AArch64, but it doesn't have reg constraints.
So, just with an example. I have the following C code:
void test()
{
int a = 1; int b = 2; int c = 3; int d = 4;
a++; b++; c++; d++;
}
Without any frontend optimization is compiles