search for: ecdl

Displaying 19 results from an estimated 19 matches for "ecdl".

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2013 Apr 30
3
[LLVMdev] Improving the usability of LNT
...t Steps: Add a Geomean button to plot the geomean of all the workloads instead of separate plots for each workload. If you feel that some of these improvements are valuable, then I can create patches and upload them in Phabricator for review. Thanks! With regards, Sriram -- Sriram Murali SSG/DPD/ECDL/DMP +1 (519) 772 - 2579 -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20130430/4bc62159/attachment.html>
2012 Jan 20
1
[LLVMdev] Public SmallVectorImpl constructor?
...first argument is a SmallVectorImpl<char>). A note in the docs about not using SmallVectorImpl directly would be nice but could we go further and make SmallVectorImpl’s constructors not public? Is there a reason why they’re public right now? -- Edwin Vane Software Developer SSG/DPD/ECDL/ArBB Phone: +1 519 772 2567 iNET: 87722567 -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20120120/401b8f99/attachment.html>
2013 Sep 27
2
[LLVMdev] Trip count and Loop Vectorizer
...nt. Loop unrolling is disabled when TC > 0. Should this be changed to TC >= 0 (which does the job for this testcase)? Or is there a better way to disable loop unrolling for such trivial loops, at least the ones with known array size? Thanks for your feedback Sriram -- Sriram Murali SSG/DPD/ECDL/DMP +1 (519) 772 - 2579 -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20130927/da13069f/attachment.html>
2013 Apr 15
1
[LLVMdev] State of Loop Unrolling and Vectorization in LLVM
...e performance difference on gcc against clang Gcc - 8.6 seconds Clang - 12.7 seconds Evidently, the addition operation can be vectorized to use addps, (clang does addss), and the loop can be unrolled for better performance. Any idea why this is happening ? Thanks Sriram -- Sriram Murali SSG/DPD/ECDL/DMP +1 (519) 772 - 2579 -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20130415/ff0af6dc/attachment.html>
2012 Apr 09
1
[LLVMdev] Question about CriticalAntiDepBreaker.cpp
...T instruction. Could one of you tell me where in the LLVM source code I should be looking to find where function return registers are set up such that the critical anti-dependency code can notice them? Thanks, Preston -- Preston Gurd <preston.gurd at intel.com> Intel Waterloo SSG/DPD/ECDL/DMP
2012 Sep 20
1
[LLVMdev] How to locate the start if an address mode in an X86 MachineInstr?
...print out the operands for a particular class of instruction. Would you know if there is a way, given a MachineInstr, to obtain the address offset? Or, if not, could you sketch out a way to do that? Thanks, Preston -- Preston Gurd <preston.gurd at intel.com> Intel Waterloo SSG/DPD/ECDL/DMP
2013 May 02
0
[LLVMdev] Improving the usability of LNT
...you feel that some of these improvements are valuable, then I can > create patches and upload them in Phabricator for review.**** > > Thanks!**** > > ** ** > > With regards,**** > > Sriram**** > > ** ** > > --**** > > Sriram Murali**** > > SSG/DPD/ECDL/DMP**** > > +1 (519) 772 – 2579**** > > ** ** > > _______________________________________________ > LLVM Developers mailing list > LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev > > -------------- next part...
2013 Sep 27
0
[LLVMdev] Trip count and Loop Vectorizer
...0. Should this be changed to TC >= 0 (which does the job for this testcase)? Or is there a better way to disable loop unrolling for such trivial loops, at least the ones with known array size? > > Thanks for your feedback > > Sriram > > -- > Sriram Murali > SSG/DPD/ECDL/DMP > +1 (519) 772 – 2579 > > _______________________________________________ > LLVM Developers mailing list > LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev -------------- next part -------------- An HTML attachment w...
2012 Nov 26
2
[LLVMdev] RFC: change BoundsChecking.cpp to use address-based tests
...ress-based testing (with one wart that makes it not production grade) but not done benchmarking and analysis. Before I do that, I'm looking for any reasons that this method of bounds checking would be a "no go". -- Kevin Schoedel kevin.p.schoedel at intel.com +1-519-772-2580 SSG-DPD-ECDL-DMP - Intel Dynamic Mobility and Parallelism
2013 Sep 27
2
[LLVMdev] Trip count and Loop Vectorizer
...nt. Loop unrolling is disabled when TC > 0. Should this be changed to TC >= 0 (which does the job for this testcase)? Or is there a better way to disable loop unrolling for such trivial loops, at least the ones with known array size? Thanks for your feedback Sriram -- Sriram Murali SSG/DPD/ECDL/DMP +1 (519) 772 - 2579 _______________________________________________ LLVM Developers mailing list LLVMdev at cs.uiuc.edu<mailto:LLVMdev at cs.uiuc.edu> http://llvm.cs.uiuc.edu<http://llvm.cs.uiuc.edu/> http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev -------------- next pa...
2012 Dec 04
2
[LLVMdev] RFC: change BoundsChecking.cpp to use address-based tests
...production grade) but not done benchmarking and analysis. Before >> I do that, I'm looking for any reasons that this method of bounds >> checking would be a "no go". >> >> -- >> Kevin Schoedel kevin.p.schoedel at intel.com +1-519-772-2580 >> SSG-DPD-ECDL-DMP - Intel Dynamic Mobility and Parallelism > > _______________________________________________ > LLVM Developers mailing list > LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev
2012 Nov 26
0
[LLVMdev] RFC: change BoundsChecking.cpp to use address-based tests
...that makes it > not production grade) but not done benchmarking and analysis. Before > I do that, I'm looking for any reasons that this method of bounds > checking would be a "no go". > > -- > Kevin Schoedel kevin.p.schoedel at intel.com +1-519-772-2580 > SSG-DPD-ECDL-DMP - Intel Dynamic Mobility and Parallelism
2012 Jan 20
0
[LLVMdev] Public SmallVectorImpl constructor?
...st argument is a SmallVectorImpl<char>). A note in the docs about not using SmallVectorImpl directly would be nice but could we go further and make SmallVectorImpl's constructors not public? Is there a reason why they're public right now? -- Edwin Vane Software Developer SSG/DPD/ECDL/ArBB Phone: +1 519 772 2567 iNET: 87722567 -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20120120/7ed97847/attachment.html>
2012 Apr 09
0
[LLVMdev] (no subject)
-- Preston Gurd <preston.gurd at intel.com> Intel Waterloo SSG/DPD/ECDL/DMP -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20120409/b78a88d6/attachment.html>
2013 Feb 13
2
[LLVMdev] TargetSpec
...out OS's etc. The problem here is that tblgen depends on Support. I'm looking for guidance on the right thing to do here, and (depending on the answer) possibly some suggestions on getting the build systems to do it. -- Kevin Schoedel kevin.p.schoedel at intel.com +1-519-772-2580 SSG-DPD-ECDL-DMP - Intel Dynamic Mobility and Parallelism
2012 Dec 04
0
[LLVMdev] RFC: change BoundsChecking.cpp to use address-based tests
Hi, > Could you provide a bit of background of the expected domains of Size and > Offset? In particular, are they signed or unsigned integers? A > non-negative size doesn't seem to make much sense in this context, but > depending on how it's calculated I could see it arising. Is a zero Size > something that might arise here? I'm assuming the Offset comes from an
2012 Jul 26
1
[LLVMdev] Question about ExpandPostRAPseudos.cpp
...veness checking fails in MachineVerifier.cpp. Would anyone be able to comment on why the SUBREG_TO_REG conversion changes the destination register and/or to suggest how this problem might best be fixed? Thanks! Preston -- Preston Gurd <preston.gurd at intel.com> Intel Waterloo SSG/DPD/ECDL/DMP -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20120726/2ceaa157/attachment.html>
2013 Sep 27
0
[LLVMdev] Trip count and Loop Vectorizer
...0. Should this be changed to TC >= 0 (which does the job for this testcase)? Or is there a better way to disable loop unrolling for such trivial loops, at least the ones with known array size? > > Thanks for your feedback > > Sriram > > -- > Sriram Murali > SSG/DPD/ECDL/DMP > +1 (519) 772 – 2579 > > _______________________________________________ > LLVM Developers mailing list > LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev > > _______________________________________________ &...
2013 Feb 28
2
[LLVMdev] Calling with register indirect reference instead of memory indirect reference.
...#39; failed. 0 llc 0x000000000117ef3a llvm::sys::PrintStackTrace(_IO_FILE*) + 38 I am wondering if the modification made to the DAG is causing a problem, and can it be done at all? If I cannot do this, is there any other place I can look at, to make this work. -- Sriram Murali SSG/DPD/ECDL/DMP +1 (519) 772 - 2579 -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20130228/426de877/attachment.html> -------------- next part -------------- A non-text attachment was scrubbed... Name: call_indirect_r...