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But isn't kinda silly that we transform to xor and then we transform it back. What is the advantage in doing so? Also, since we do that method, I now have to introduce setcc patterns for i1 values, instead of being able to just use logical pattern operators like not. -Dilan On Fri, Jul 21, 2017 at 11:00 AM Dilan Manatunga <manatunga at gmail.com> wrote: > For some reason I didn't get Krzysztof Parzyszek e-mail in my inbox, but > thanks for the fact I can override the getSetCCResultType. Didn't even > think of that. > > -Dilan > > O...

Thanks that clears things up. So if I want to mess around with how schedules are generated, looking at the MachineScheduler pass is the best place now? -Dilan On Mon, Jul 31, 2017 at 3:24 PM Matthias Braun <mbraun at apple.com> wrote: > > > On Jul 31, 2017, at 2:51 PM, Dilan Manatunga via llvm-dev < > llvm-dev at lists.llvm.org> wrote: > > > > Hi, > > > > I was looking into how SelectionDAG scheduling is...

...%conv, %conv1 %conv2 = trunc i32 %div to i16 * Assume %0 and %1 are registers created from simple 16-bit loads. We cannot reduce the sequence to: %div = sdiv i16 %0 %1 What is the reason for the exclusion of sdiv from the operations considered valid for execution in a truncated format. Thanks, -Dilan Manatunga -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20160531/2d3ea4b6/attachment.html>

Ohh, that makes sense. And is the reason the first instruction doesn't get deleted because the ExpandPseudoInstructions pass occurs after Register Allocation and machine dead code elimination? -Dilan On Fri, Jul 7, 2017 at 12:37 PM Friedman, Eli <efriedma at codeaurora.org> wrote: > On 7/7/2017 12:10 PM, Dilan Manatunga wrote: > > My bad for not looking further. I'm still somewhat confused though. > > MOVCCr gets expanded in the ARMExpandPseudoInsts pass, and it still...

...MOVCCr gets expanded in the ARMExpandPseudoInsts pass, and it still seems only a case of one instruction replacing the other. My worry of emitting two instructions, is that a dead code pass will eliminate the first instruction cause it thinks the second instruction is defining the same register. -Dilan On Fri, Jul 7, 2017 at 11:20 AM Friedman, Eli <efriedma at codeaurora.org> wrote: > On 7/7/2017 11:12 AM, Dilan Manatunga via llvm-dev wrote: > > Hi, > > > > I was wondering what would be the best way to lower a select operation > > two predicated movs. I looked t...

...inters. Well, to my questions I guess. Why is this happening? Isn't it kinda silly to convert a setcc to an xor, and then convert it back to a slightly different output setcc. And how can I prevent this, or fix it, since my conditional branches only support having single bit inputs. Thanks, -Dilan PS Here is optimized DAG in case you were wondering. Combining: t0: ch = EntryToken Optimized legalized selection DAG: BB#212 'merge_sort:for.cond.cleanup39.1' SelectionDAG has 36 nodes: t0: ch = EntryToken t6: i32,ch = CopyFromReg t0, Register:i32 %vreg507 t2: i32,ch = CopyFromReg t0, Re...

...ng what would be the best way to lower a select operation two predicated movs. I looked through the ARM, MIPS, and NVPTX backends and they all seem to lower a select to some sort of conditional move or native select operation. Ex. select t3, cond, t2, t1 Becomes cond mov t3, t2 !cond mov t3, t1 -Dilan -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20170707/a7c3db47/attachment.html>

...dition calculation, and the branch). Right now, I thought of using the loop pass to somehow mark the instructions that should be lowered to a loop instruction, and translating them in the selection phase, but I'm not entirely sure how to do that or if that is even the right strategy. Thanks, -Dilan Manatunga -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20160602/43e5524a/attachment.html>

...ending on architecture, in the end, it ends up using source scheduling. I realized this is because it overrides enableMachineScheduler to return true. Is there any specific reasons why it was done this way, and also, what happens to be class mainly responsible for the X86 scheduling then? Thanks, -Dilan -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20170731/999f5ffa/attachment.html>

...lacement to change these instructions, but I am wondering if there is a recommended way to do this. Especially as this seems like a common problem, where an existing generic pass would have some interface a backend should support to allow branch re-writes to create the single branch case. Thanks, -Dilan -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20170709/dfe6d347/attachment.html>

On 31 May 2016 at 16:02, Dilan Manatunga <manatunga at gmail.com> wrote: > Just to verify, a 16-bit divion of INT16_MIN by -1 results in INT16_MIN > again? No, "sdiv i16 -32768, -1" is undefined behaviour. The version with an "sext" and "trunc" avoids the undefined behaviour and does r...

Hi Dilan, On 31 May 2016 at 15:34, Dilan Manatunga via llvm-dev <llvm-dev at lists.llvm.org> wrote: > What is the reason for the exclusion of sdiv from the operations considered > valid for execution in a truncated format. A 16-bit division of INT16_MIN by -1 is undefined behaviour but the ori...

On 31 May 2016 at 15:42, Tim Northover <t.p.northover at gmail.com> wrote: > A 16-bit division of INT16_MIN by -1 is undefined behaviour but the > original ext/trunc version is well-defined as 0. Sorry, INT16_MIN again actually. The main point still stands though, I think. Tim.

...the issue only occurs in this case, why aren't there checks to see if we can simplify sdiv in cases where we know that numerator is not INT16_MIN or the denominator is not -1. For example, we could simplify divides involving one operand constants. Is it because this case is most likely rare? -Dilan On Tue, May 31, 2016 at 3:50 PM Tim Northover <t.p.northover at gmail.com> wrote: > On 31 May 2016 at 15:42, Tim Northover <t.p.northover at gmail.com> wrote: > > A 16-bit division of INT16_MIN by -1 is undefined behaviour but the > > original ext/trunc version is well-...

...o know if the syntax I have used in the predictors is right for the split plot model. If not, how do I give the split plot model in R. summary(bmod) does not give any p-values for individual tests or a degrees of freedom to test them. How do I test these factors using the vglm function? Thank you Dilan Paranagama