Displaying 20 results from an estimated 519 matches for "dev_priv".
Did you mean:
ndev_priv
2010 Feb 25
3
[PATCH 1/3] drm/nv50: Implement ctxprog/state generation.
...quot;nouveau/nva8.ctxvals");
-MODULE_FIRMWARE("nouveau/nvaa.ctxprog");
-MODULE_FIRMWARE("nouveau/nvaa.ctxvals");
-MODULE_FIRMWARE("nouveau/nvac.ctxprog");
-MODULE_FIRMWARE("nouveau/nvac.ctxvals");
+#include "nouveau_grctx.h"
#define IS_G80 ((dev_priv->chipset & 0xf0) == 0x50)
@@ -111,9 +88,34 @@ nv50_graph_init_ctxctl(struct drm_device *dev)
NV_DEBUG(dev, "\n");
- nouveau_grctx_prog_load(dev);
- if (!dev_priv->engine.graph.ctxprog)
- dev_priv->engine.graph.accel_blocked = true;
+ if (nouveau_ctxfw) {
+ nouveau_g...
2009 Dec 19
1
[PATCH] drm/nouveau: always do buffer object moves on bo->channel
...return chan->vram_handle;
+ return NvDmaGART;
+ return NvDmaVRAM;
}
static int
@@ -495,22 +489,11 @@ nouveau_bo_move_m2mf(struct ttm_buffer_object *bo, int evict, bool intr,
int ret;
chan = nvbo->channel;
- if (!chan || nvbo->tile_flags || nvbo->no_vm)
+ if (!chan)
chan = dev_priv->channel;
src_offset = old_mem->mm_node->start << PAGE_SHIFT;
dst_offset = new_mem->mm_node->start << PAGE_SHIFT;
- if (chan != dev_priv->channel) {
- if (old_mem->mem_type == TTM_PL_TT)
- src_offset += dev_priv->vm_gart_base;
- else
- src_offset += d...
2010 Feb 07
3
[PATCH] drm/nouveau: don't hold spin lock while calling kzalloc with GFP_KERNEL
.../nouveau/nouveau_channel.c
index d25ed61..f7ca950 100644
--- a/drivers/gpu/drm/nouveau/nouveau_channel.c
+++ b/drivers/gpu/drm/nouveau/nouveau_channel.c
@@ -113,7 +113,6 @@ nouveau_channel_alloc(struct drm_device *dev, struct nouveau_channel **chan_ret,
struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
struct nouveau_channel *chan;
- unsigned long flags;
int channel, user;
int ret;
@@ -204,8 +203,6 @@ nouveau_channel_alloc(struct drm_device *dev, struct nouveau_channel **chan_ret,
return ret;
}
-...
2009 Jul 25
2
[RFC] patch 0/4: DRM MMIO accessor cleanup
Hi,
this is continuation for the MMIO accessor rewrite and cleanup.
I am currently running nv28 with these patches applied, but
I cannot test on PPC.
Please, review and comment. If the direction is good, I'll do the
same to INSTANCE_{RD,WR} as I did for nv_{rd,wr}32, and change
PRAMIN from drm_local_map to simple ioremap.
Can the same be done for channel specific mappings, that is
2009 Aug 19
1
[PATCH] drm/nouveau: Add a MM for mappable VRAM that isn't usable as scanout.
...LAG_NEEDS_IOREMAP;
+ man->available_caching = TTM_PL_FLAG_UNCACHED |
+ TTM_PL_FLAG_WC;
+ man->default_caching = TTM_PL_FLAG_WC;
+
+ man->io_addr = NULL;
+ man->io_offset = drm_get_resource_start(dev, 1);
+ man->io_size = drm_get_resource_len(dev, 1);
+ man->gpu_offset = dev_priv->vm_vram_base;
+ break;
+ }
case TTM_PL_TT:
switch (dev_priv->gart_info.type) {
case NOUVEAU_GART_AGP:
@@ -564,6 +582,7 @@ nouveau_bo_verify_access(struct ttm_buffer_object *bo, struct file *filp)
static uint32_t nouveau_mem_prios[] = {
TTM_PL_PRIV0,
+ TTM_PL_PRIV1,
TTM_PL_VR...
2009 Nov 19
2
[RFC] nouveau: Add basic i2c sensor chip support
...le(dev, bios, bitoffset, &BIT_TABLE('P', performance));
return 0;
}
@@ -5252,6 +5302,7 @@ static int parse_dcb_table(struct drm_device *dev, struct nvbios *bios, bool two
{
struct bios_parsed_dcb *bdcb = &bios->bdcb;
struct parsed_dcb *dcb;
+ struct drm_nouveau_private *dev_priv = dev->dev_private;
uint16_t dcbptr, i2ctabptr = 0;
uint8_t *dcbtable;
uint8_t headerlen = 0x4, entries = DCB_MAX_NUM_ENTRIES;
@@ -5357,8 +5408,19 @@ static int parse_dcb_table(struct drm_device *dev, struct nvbios *bios, bool two
NV_WARN(dev, "No pointer to DCB I2C port table\n&qu...
2012 Apr 25
5
[PATCH v2 4/4] drm/nouveau: gpu lockup recovery
...veau/nouveau_bo.c
index 5b0dc50..7de6cad 100644
--- a/drivers/gpu/drm/nouveau/nouveau_bo.c
+++ b/drivers/gpu/drm/nouveau/nouveau_bo.c
@@ -936,7 +936,7 @@ nouveau_bo_move(struct ttm_buffer_object *bo, bool evict, bool intr,
}
/* Software copy if the card isn't up and running yet. */
- if (!dev_priv->channel) {
+ if (!dev_priv->channel || nouveau_gpu_reset_in_progress(dev_priv->dev)) {
ret = ttm_bo_move_memcpy(bo, evict, no_wait_reserve, no_wait_gpu, new_mem);
goto out;
}
diff --git a/drivers/gpu/drm/nouveau/nouveau_channel.c b/drivers/gpu/drm/nouveau/nouveau_channel.c
index 8...
2020 Apr 15
1
[PATCH 27/59] drm/qxl: Don't use drm_device->dev_private
...644
--- a/drivers/gpu/drm/qxl/qxl_debugfs.c
+++ b/drivers/gpu/drm/qxl/qxl_debugfs.c
@@ -39,7 +39,7 @@ static int
qxl_debugfs_irq_received(struct seq_file *m, void *data)
{
struct drm_info_node *node = (struct drm_info_node *) m->private;
- struct qxl_device *qdev = node->minor->dev->dev_private;
+ struct qxl_device *qdev = to_qxl(node->minor->dev);
seq_printf(m, "%d\n", atomic_read(&qdev->irq_received));
seq_printf(m, "%d\n", atomic_read(&qdev->irq_received_display));
@@ -53,7 +53,7 @@ static int
qxl_debugfs_buffers_info(struct seq_file *m...
2020 Apr 03
1
[PATCH 31/44] drm/qxl: Don't use drm_device->dev_private
...644
--- a/drivers/gpu/drm/qxl/qxl_debugfs.c
+++ b/drivers/gpu/drm/qxl/qxl_debugfs.c
@@ -39,7 +39,7 @@ static int
qxl_debugfs_irq_received(struct seq_file *m, void *data)
{
struct drm_info_node *node = (struct drm_info_node *) m->private;
- struct qxl_device *qdev = node->minor->dev->dev_private;
+ struct qxl_device *qdev = to_qxl(node->minor->dev);
seq_printf(m, "%d\n", atomic_read(&qdev->irq_received));
seq_printf(m, "%d\n", atomic_read(&qdev->irq_received_display));
@@ -53,7 +53,7 @@ static int
qxl_debugfs_buffers_info(struct seq_file *m...
2012 Apr 22
2
[RFC PATCH 5/5] drm/nouveau: gpu lockup recovery
...veau/nouveau_bo.c
index 5b0dc50..7de6cad 100644
--- a/drivers/gpu/drm/nouveau/nouveau_bo.c
+++ b/drivers/gpu/drm/nouveau/nouveau_bo.c
@@ -936,7 +936,7 @@ nouveau_bo_move(struct ttm_buffer_object *bo, bool evict, bool intr,
}
/* Software copy if the card isn't up and running yet. */
- if (!dev_priv->channel) {
+ if (!dev_priv->channel || nouveau_gpu_reset_in_progress(dev_priv->dev)) {
ret = ttm_bo_move_memcpy(bo, evict, no_wait_reserve, no_wait_gpu, new_mem);
goto out;
}
diff --git a/drivers/gpu/drm/nouveau/nouveau_channel.c b/drivers/gpu/drm/nouveau/nouveau_channel.c
index 8...
2009 Dec 11
5
[PATCH 1/3] drm/nouveau: Pre-G80 tiling support.
.../nouveau/nv10_fb.c
+++ b/drivers/gpu/drm/nouveau/nv10_fb.c
@@ -3,17 +3,37 @@
#include "nouveau_drv.h"
#include "nouveau_drm.h"
+void
+nv10_fb_set_region_tiling(struct drm_device *dev, int i, uint32_t addr,
+ uint32_t size, uint32_t pitch)
+{
+ struct drm_nouveau_private *dev_priv = dev->dev_private;
+ uint32_t limit = max(1u, addr + size) - 1;
+
+ if (pitch) {
+ if (dev_priv->card_type >= NV_20)
+ addr |= 1;
+ else
+ addr |= 1 << 31;
+ }
+
+ nv_wr32(dev, NV10_PFB_TLIMIT(i), limit);
+ nv_wr32(dev, NV10_PFB_TSIZE(i), pitch);
+ nv_wr32(dev, NV10_PFB_TILE(i...
2010 Jun 01
1
"typo" in "drm/nv50: cast IGP memory location to u64 before shifting"
...is does not look right:
diff --git a/drivers/gpu/drm/nouveau/nouveau_mem.c b/drivers/gpu/drm/nouveau/nouveau_mem.c
index 775a701..c1fd42b 100644
--- a/drivers/gpu/drm/nouveau/nouveau_mem.c
+++ b/drivers/gpu/drm/nouveau/nouveau_mem.c
@@ -540,7 +540,8 @@ nouveau_mem_detect(struct drm_device *dev)
dev_priv->vram_size = nv_rd32(dev, NV04_FIFO_DATA);
dev_priv->vram_size &= NV10_FIFO_DATA_RAM_AMOUNT_MB_MASK;
if (dev_priv->chipset == 0xaa || dev_priv->chipset == 0xac)
- dev_priv->vram_sys_base = nv_rd32(dev, 0x100e10) << 12;
+ dev_priv->vram_sys_base = nv_rd32(dev,...
2009 Feb 18
1
[PATCH] Add in-kernel backlight control support
...linux/backlight.h>
+
+#include "drmP.h"
+#include "nouveau_drv.h"
+#include "nouveau_drm.h"
+#include "nouveau_reg.h"
+
+static int nv40_get_intensity(struct backlight_device *bd)
+{
+ struct drm_device *dev = bl_get_data(bd);
+ struct drm_nouveau_private *dev_priv = dev->dev_private;
+ int val = (NV_READ(NV40_PMC_BACKLIGHT) & NV40_PMC_BACKLIGHT_MASK) >> 16;
+
+ return val;
+}
+
+static int nv40_set_intensity(struct backlight_device *bd)
+{
+ struct drm_device *dev = bl_get_data(bd);
+ struct drm_nouveau_private *dev_priv = dev->dev_private;
+...
2010 Feb 01
4
[PATCH 1/3] Introduce nouveau_bo_wait for waiting on a BO with a GPU channel
nouveau_bo_wait will make the GPU channel wait for fence if possible,
otherwise falling back to waiting with the CPU using ttm_bo_wait.
The nouveau_fence_sync function currently returns -ENOSYS, and is
the focus of the next patch.
Signed-off-by: Luca Barbieri <luca at luca-barbieri.com>
---
drivers/gpu/drm/nouveau/nouveau_bo.c | 68 ++++++++++++++++++++++++++++++-
2009 Aug 02
3
[PATCH 1/4] drm/nouveau: refactor VGA font save/restore
..., unsigned reg, u8 val)
#define nv_wait(reg,mask,val) nouveau_wait_until(dev, 2000000000ULL, (reg), \
(mask), (val))
-/*
- * VRAM access for the first 64kB
- * see nouveau_state.c
- */
-static inline u32 nv_rf32(struct drm_device *dev, unsigned offset)
-{
- struct drm_nouveau_private *dev_priv = dev->dev_private;
- return ioread32_native(dev_priv->fb + offset);
-}
-
-static inline void nv_wf32(struct drm_device *dev, unsigned offset, u32 val)
-{
- struct drm_nouveau_private *dev_priv = dev->dev_private;
- iowrite32_native(val, dev_priv->fb + offset);
-}
-
/* PRAMIN access */...
2011 Nov 06
0
[PATCH] drm/nouveau: add nouveau.vram_limit module option
...uveau_mem.c
index 36bec48..3330d6c 100644
--- a/drivers/gpu/drm/nouveau/nouveau_mem.c
+++ b/drivers/gpu/drm/nouveau/nouveau_mem.c
@@ -240,6 +240,21 @@ nouveau_mem_detect_nforce(struct drm_device *dev)
return 0;
}
+void nouveau_limit_vram(struct drm_device *dev)
+{
+ struct drm_nouveau_private *dev_priv = dev->dev_private;
+ u64 tmp;
+ if (!nouveau_vram_limit)
+ return;
+
+ tmp = min((u64)(nouveau_vram_limit << 20), dev_priv->vram_size);
+ if (tmp != dev_priv->vram_size) {
+ NV_INFO(dev, "limiting size of VRAM to %d MiB (from %d MiB)\n",
+ (int)(tmp >> 20), (int...
2008 Mar 09
0
[PATCH 4/4] nouveau: clean up nouveau_mem_alloc function
...eak;
+ };
+ if (err)
+ goto error;
+
+ return block;
+error:
+ nouveau_mem_free_block(block);
+ return NULL;
+}
+
+static struct mem_block *
+nouveau_mem_alloc_pci(struct drm_device *dev, uint64_t size, int alignment,
+ int flags, struct drm_file *file_priv)
+{
+ struct drm_nouveau_private *dev_priv = dev->dev_private;
+
+ return __nouveau_mem_alloc(dev, NOUVEAU_MEM_PCI, dev_priv->pci_heap,
+ size, alignment, flags, file_priv);
+}
+
+static struct mem_block *
+nouveau_mem_alloc_agp(struct drm_device *dev, uint64_t size, int alignment,
+ int flags, struct drm_file *file_priv)...
2010 Feb 09
2
[PATCH 1/3] Introduce nouveau_bo_wait for waiting on a BO with a GPU channel (v2)
Changes in v2:
- Addressed review comments
nouveau_bo_wait will make the GPU channel wait for fence if possible,
otherwise falling back to waiting with the CPU using ttm_bo_wait.
The nouveau_fence_sync function currently returns -ENOSYS, and is
the focus of the next patch.
Signed-off-by: Luca Barbieri <luca at luca-barbieri.com>
---
drivers/gpu/drm/nouveau/nouveau_bo.c | 68
2012 Feb 03
3
[PATCH 1/4] nouveau: Allow allocating BOs at specific offsets
...gn,
+nouveau_bo_new(struct drm_device *dev, int base, int size, int align,
uint32_t flags, uint32_t tile_mode, uint32_t tile_flags,
struct nouveau_bo **pnvbo)
{
@@ -119,10 +119,16 @@ nouveau_bo_new(struct drm_device *dev, int size, int align,
acc_size = ttm_bo_dma_acc_size(&dev_priv->ttm.bdev, size,
sizeof(struct nouveau_bo));
+ if (base) {
+ nvbo->placement.fpfn = base >> PAGE_SHIFT;
+ nvbo->placement.lpfn = dev_priv->vram_size >> PAGE_SHIFT;
+ }
+
ret = ttm_bo_init(&dev_priv->ttm.bdev, &nvbo->bo, size,
ttm_bo_type...
2012 Jul 27
0
[PATCH 3/3] nouveau: add vblank methods on newer cards
...au/nouveau_display.c b/drivers/gpu/drm/nouveau/nouveau_display.c
index 69688ef..fa0cf14 100644
--- a/drivers/gpu/drm/nouveau/nouveau_display.c
+++ b/drivers/gpu/drm/nouveau/nouveau_display.c
@@ -364,7 +364,9 @@ nouveau_vblank_enable(struct drm_device *dev, int crtc)
{
struct drm_nouveau_private *dev_priv = dev->dev_private;
- if (dev_priv->card_type >= NV_50)
+ if (dev_priv->card_type >= NV_D0)
+ nv_mask(dev, 0x6100c0 + (crtc * 0x800), 0x5, 0x5);
+ else if (dev_priv->card_type >= NV_50)
nv_mask(dev, NV50_PDISPLAY_INTR_EN_1, 0,
NV50_PDISPLAY_INTR_EN_1_VBLANK_CRTC_(crtc...