search for: desmalen

Displaying 20 results from an estimated 24 matches for "desmalen".

2020 May 19
3
LV: predication
...0 09:56 To: Sjoerd Meijer <Sjoerd.Meijer at arm.com> Cc: Roger Ferrer Ibáñez <rofirrim at gmail.com>; Eli Friedman <efriedma at quicinc.com>; listmail at philipreames.com <listmail at philipreames.com>; llvm-dev <llvm-dev at lists.llvm.org>; Sander De Smalen <Sander.DeSmalen at arm.com>; hanna.kruppe at gmail.com <hanna.kruppe at gmail.com> Subject: Re: [llvm-dev] LV: predication Hi Sjoerd, On 5/18/20 3:43 PM, Sjoerd Meijer wrote: > You have similar problems with https://reviews.llvm.org/D79100 The new revision D79100<https://reviews.llvm.org/D79100&g...
2020 May 19
2
LV: predication
...0 15:07 To: Sjoerd Meijer <Sjoerd.Meijer at arm.com> Cc: Roger Ferrer Ibáñez <rofirrim at gmail.com>; Eli Friedman <efriedma at quicinc.com>; listmail at philipreames.com <listmail at philipreames.com>; llvm-dev <llvm-dev at lists.llvm.org>; Sander De Smalen <Sander.DeSmalen at arm.com>; hanna.kruppe at gmail.com <hanna.kruppe at gmail.com> Subject: Re: [llvm-dev] LV: predication On 5/19/20 12:38 PM, Sjoerd Meijer wrote: Hi Simon, Thanks for reposting the example, and looking at it more carefully, I think it is very similar to my first proposal. This was met...
2020 May 18
2
LV: predication
...0 14:11 To: Sjoerd Meijer <Sjoerd.Meijer at arm.com> Cc: Roger Ferrer Ibáñez <rofirrim at gmail.com>; Eli Friedman <efriedma at quicinc.com>; listmail at philipreames.com <listmail at philipreames.com>; llvm-dev <llvm-dev at lists.llvm.org>; Sander De Smalen <Sander.DeSmalen at arm.com>; hanna.kruppe at gmail.com <hanna.kruppe at gmail.com> Subject: Re: [llvm-dev] LV: predication On 5/18/20 2:53 PM, Sjoerd Meijer wrote: Hi, I abandoned that approach and followed Eli's suggestion, see somewhere earlier in this thread, and emit an intrinsic that represents/...
2019 Dec 16
2
SVE/SVE2 LLVM sync-up calls
...better coordinate our efforts and to have a collated list of open SVE/SVE2 patches on Phabricator. I'll try to keep this list up-to-date! https://docs.google.com/document/d/1ph1l1KhrrHgBlrKeEnuoIPrVO9jTjHvcwUlz61QWNMA Cheers, Sander > On 5 Dec 2019, at 22:44, Sander De Smalen <Sander.DeSmalen at arm.com> wrote: > > Thanks to everyone who filled in the Doodle poll! > > The first SVE/SVE2 LLVM sync-up call will be held on: > Thursday 12 Dec, 4pm GMT / 8am PST > > Please add your name and email address to the document linked below, so I can forward the meeting i...
2020 May 18
2
LV: predication
...0 13:32 To: Sjoerd Meijer <Sjoerd.Meijer at arm.com> Cc: Roger Ferrer Ibáñez <rofirrim at gmail.com>; Eli Friedman <efriedma at quicinc.com>; listmail at philipreames.com <listmail at philipreames.com>; llvm-dev <llvm-dev at lists.llvm.org>; Sander De Smalen <Sander.DeSmalen at arm.com>; hanna.kruppe at gmail.com <hanna.kruppe at gmail.com> Subject: Re: [llvm-dev] LV: predication On 5/5/20 12:07 AM, Sjoerd Meijer via llvm-dev wrote: what we would like to generate is a vector loop with implicit predication, which works by setting up the the number of elements...
2019 Dec 03
2
SVE/SVE2 LLVM sync-up calls
Hi all, Several people have expressed interest in having regular sync-up calls to follow the progress of ARM SVE/SVE2 support in LLVM. With this effort picking up steam and multiple people contributing patches, regular sync-up calls would provide a platform to coordinate our efforts. Items to discuss in these sync-up calls would include: - SVE/SVE2 CodeGen support - Adding support for C/C++
2018 Jan 09
1
RFC: [LV] any objections in moving isLegalMasked* check from Legal to CostModel? (Cleaning up LoopVectorizationLegality)
...lt;estotzer at ti.com>; Nemanja Ivanovic <nemanja.i.ibm at gmail.com>; Kreitzer, David L <david.l.kreitzer at intel.com>; Nuzman, Dorit <dorit.nuzman at intel.com>; Adam Nemet <anemet at apple.com>; James Molloy <James.Molloy at arm.com>; Sander De Smalen <Sander.DeSmalen at arm.com>; Zaks, Ayal <ayal.zaks at intel.com>; Graham Hunter <Graham.Hunter at arm.com>; Michael Kuperstein <mkuper at google.com>; Caballero, Diego <diego.caballero at intel.com>; Sanjay Patel <spatel at rotateright.com>; Simon Pilgrim <llvm-dev at redking.me...
2018 Jan 06
2
RFC: [LV] any objections in moving isLegalMasked* check from Legal to CostModel? (Cleaning up LoopVectorizationLegality)
...lt;estotzer at ti.com>; Nemanja Ivanovic <nemanja.i.ibm at gmail.com>; Kreitzer, David L <david.l.kreitzer at intel.com>; Nuzman, Dorit <dorit.nuzman at intel.com>; Adam Nemet <anemet at apple.com>; James Molloy <James.Molloy at arm.com>; Sander De Smalen <Sander.DeSmalen at arm.com>; Zaks, Ayal <ayal.zaks at intel.com>; Graham Hunter <Graham.Hunter at arm.com>; Michael Kuperstein <mkuper at google.com>; Caballero, Diego <diego.caballero at intel.com>; Sanjay Patel <spatel at rotateright.com>; Simon Pilgrim <llvm-dev at redking.me...
2018 Jan 07
0
RFC: [LV] any objections in moving isLegalMasked* check from Legal to CostModel? (Cleaning up LoopVectorizationLegality)
...lt;estotzer at ti.com>; Nemanja Ivanovic <nemanja.i.ibm at gmail.com>; Kreitzer, David L <david.l.kreitzer at intel.com>; Nuzman, Dorit <dorit.nuzman at intel.com>; Adam Nemet <anemet at apple.com>; James Molloy <James.Molloy at arm.com>; Sander De Smalen <Sander.DeSmalen at arm.com>; Zaks, Ayal <ayal.zaks at intel.com>; Graham Hunter <Graham.Hunter at arm.com>; Michael Kuperstein <mkuper at google.com>; Caballero, Diego <diego.caballero at intel.com>; Sanjay Patel <spatel at rotateright.com>; Simon Pilgrim <llvm-dev at redking.me...
2020 Nov 12
0
An update on scalable vectors in LLVM
...t has reached consensus across different companies and industries. We're finally discussing high level vectorisation strategies without having to worry about the mechanics of scalable vector representation. This is a big long term win. On Wed, 11 Nov 2020 at 22:06, Sander De Smalen <Sander.DeSmalen at arm.com> wrote: > We (Arm) prefer starting out with adding support for 1 in upstream LLVM, > because it is the easiest to support and gives a lot of ‘bang for buck’ > that will help us incrementally add more scalable auto-vec capabilities to > the vectorizer. A proof of concept o...
2020 Jun 15
2
[AArch64][SVE] Floating Point Code Gen
Hello, I am following up on the issue discussed at the SVE meeting, Sander mentioned that there were some patterns missing from SVE CodeGen for floating point operations, but I was unable to identify them. He mentioned something about looking at the ISelLowering for AArch64 to identify them, so if there is any information of that regard it would be greatly appreciated so we can contribute with
2020 Nov 11
3
An update on scalable vectors in LLVM
Hi all, It's been a while since we've given an update on scalable vector support in LLVM. Over the last 12 months a lot of work has been done to make LLVM cope with scalable vectors. This effort is now starting to bear fruit with LLVM gaining more capabilities, including an intrinsics interface for AArch64 SVE/SVE2, LLVM IR Codegen for scalable vectors, and several loop-vectorization
2019 Oct 01
2
Adding support for vscale
...t; > (readers note this, copied from the end before writing! > "Given that (2) is a very different use-case, I hope we can keep discussions on > that model separate from this thread, if possible.") > > > On Tue, Oct 1, 2019 at 12:45 PM Sander De Smalen > <Sander.DeSmalen at arm.com> wrote: > >> Thanks @Robin and @Graham for giving some background on scalable vectors and clarifying some of the details! > > hi sander, thanks for chipping in. um, just a point of order: was it > intentional to leave out both jacob and myself? my understanding i...
2018 Jan 05
0
RFC: [LV] any objections in moving isLegalMasked* check from Legal to CostModel? (Cleaning up LoopVectorizationLegality)
> On 5 Jan 2018, at 21:01, Saito, Hideki via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > > All, > > I'm trying to refactor LoopVectorize such that it has better conformance to VPlan vision going forward > (http://www.llvm.org/docs/Proposals/VectorizationPlan.html). All VP*Recipe class definitions are now > moved to VPlan.h, and I have a patch under review
2019 Oct 01
2
Adding support for vscale
Thanks @Robin and @Graham for giving some background on scalable vectors and clarifying some of the details! Apologies if I'm repeating things here, but it is probably good to emphasize the conceptually different, but complementary models for scalable vectors: 1. Vectors of unknown, but constant size throughout the program. 2. Vectors of changing size throughout the program. Where (2)
2018 Jan 05
2
RFC: [LV] any objections in moving isLegalMasked* check from Legal to CostModel? (Cleaning up LoopVectorizationLegality)
All, I'm trying to refactor LoopVectorize such that it has better conformance to VPlan vision going forward (http://www.llvm.org/docs/Proposals/VectorizationPlan.html). All VP*Recipe class definitions are now moved to VPlan.h, and I have a patch under review to move LoopVectorizationPlanner class out of LoopVectorize.cpp (https://reviews.llvm.org/D41420). Next thing I'm working on is
2020 May 04
3
LV: predication
Hi Roger, That's a good example, that shows most of the moving parts involved here. In a nutshell, the difference is, and what we would like to make explicit, is the vector trip versus the scalar loop trip count. In your IR example, the loads/stores are predicated on a mask that is calculated from a splat induction variable, which is compared with the vector trip count. Illustrated with your
2019 May 24
2
[EXT] Re: [RFC][SVE] Supporting SIMD instruction sets with variable vector lengths
...;Joel.Jones at cavium.com>, "dag at cray.com" <dag at cray.com>, Renato Golin <renato.golin at linaro.org>, Kristof Beyls <Kristof.Beyls at arm.com>, Amara Emerson <aemerson at apple.com>, Florian Hahn <Florian.Hahn at arm.com>, Sander De Smalen <Sander.DeSmalen at arm.com>, Robin Kruppe <robin.kruppe at gmail.com>, "llvm-dev at lists.llvm.org" <llvm-dev at lists.llvm.org>, "mkuper at google.com" <mkuper at google.com>, Sjoerd Meijer <Sjoerd.Meijer at arm.com>, Sam Parker <Sam.Parker at arm.com>, Graham...
2019 May 27
2
[EXT] Re: [RFC][SVE] Supporting SIMD instruction sets with variable vector lengths
...;Joel.Jones at cavium.com>, "dag at cray.com" <dag at cray.com>, Renato Golin <renato.golin at linaro.org>, Kristof Beyls <Kristof.Beyls at arm.com>, Amara Emerson <aemerson at apple.com>, Florian Hahn <Florian.Hahn at arm.com>, Sander De Smalen <Sander.DeSmalen at arm.com>, Robin Kruppe <robin.kruppe at gmail.com>, "llvm-dev at lists.llvm.org" <llvm-dev at lists.llvm.org>, "mkuper at google.com" <mkuper at google.com>, Sjoerd Meijer <Sjoerd.Meijer at arm.com>, Sam Parker <Sam.Parker at arm.com>, Graham...
2019 Jun 03
2
[EXT] Re: [RFC][SVE] Supporting SIMD instruction sets with variable vector lengths
...;Joel.Jones at cavium.com>, "dag at cray.com" <dag at cray.com>, Renato Golin <renato.golin at linaro.org>, Kristof Beyls <Kristof.Beyls at arm.com>, Amara Emerson <aemerson at apple.com>, Florian Hahn <Florian.Hahn at arm.com>, Sander De Smalen <Sander.DeSmalen at arm.com>, Robin Kruppe <robin.kruppe at gmail.com>, "llvm-dev at lists.llvm.org" <llvm-dev at lists.llvm.org>, "mkuper at google.com" <mkuper at google.com>, Sjoerd Meijer <Sjoerd.Meijer at arm.com>, Sam Parker <Sam.Parker at arm.com>, Graham...