search for: defmi

...f value can be rematerialized with the sequence of instruction or not. Here is the code: //New function added for checking complex multi-instruction-sequence rematerializable bool LiveRangeEdit::checkComplexRematerializable(VNInfo *VNI, const MachineInstr *DefMI, unsigned int depth, AliasAnalysis *aa) { if(TII.isReMaterializablePossible(*DefMI, aa)) return false; DEBUG(dbgs() << " ComplexRemat MI: " << *DefMI); for (unsigned i = 0, e = DefMI-...

...default, when an itinerary is available, this means that all of the defined operands are available in at most 1 cycle. ARM overrides this, and provides this more-customized definition: bool ARMBaseInstrInfo:: hasLowDefLatency(const InstrItineraryData *ItinData, const MachineInstr *DefMI, unsigned DefIdx) const { if (!ItinData || ItinData->isEmpty()) return false; unsigned DDomain = DefMI->getDesc().TSFlags & ARMII::DomainMask; if (DDomain == ARMII::DomainGeneral) { unsigned DefClass = DefMI->getDesc().getSchedClass(); int DefCycle = ItinData->get...

I'm unclear how does DFAPacketizer and the scheduler know a given instruction is a load. Here is what I'm talking about Let's assume my VLIW target is described as follows: def MyTargetItineraries : ProcessorItineraries<[Slot0, Slot1], [], [ .............................. InstrItinData<RI, [InstrStage<1, [Slot0, Slot1]>]>,

...e while checking for single live def, could you please elaborate ? IIUC, for above case, tmovi8 (movs) would update cpsr n/z flags, but since it's overwritten by following instructions, it's marked as dead in both cases ? The patch just checks that only one def is live and remaining defs of DefMI are dead in reMaterializeTrivialDef, in which case I assume it should be safe to propagate value of CopyMI into DefMI ? If reMaterializeTrivialDef is not the right place to handle the transform, could you please suggest where should I look for adding it ? Thanks! Regards, Prathamesh > > Chee...

> In particular, the LoadLatency is used in defaultDefLatency: > > /// Return the default expected latency for a def based on it's opcode. > unsigned TargetInstrInfo::defaultDefLatency( > const MCSchedModel &SchedModel, const MachineInstr *DefMI) const { > if (DefMI->isTransient()) > return 0; > if (DefMI->mayLoad()) > return SchedModel.LoadLatency; > if (isHighLatencyDef(DefMI->getOpcode())) > return SchedModel.HighLatency; > return 1; > } > > > -Krzysztof > > -- > Qua...

> On Jun 28, 2017, at 5:10 PM, Quentin Colombet via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > Oh wait, vreg1 is indeed used. > Yeah, having a dead flag here sounds wrong. I mean on the instruction itself. On the bundle, that’s debatable. That would fit the semantic “if no side effect you can kill it” (here there is side effect, we define other vregs). > >> On

...either directly queries latency tables, or calls hooks. Three possible configurations are: (1) No per-opcode tables In this case, only one helper is used: unsigned TargetInstrInfo::defaultDefLatency(const MCSchedModel *SchedModel, const MachineInstr *DefMI) const; This is currently non-virtual because it is designed to directly query the fields in the SchedMachineModel tablegen class using another hook to select high latency ops: virtual bool isHighLatencyDef(int opc) const; Instructions that are not high latency default to one cycle. Example: d...

Hi Quentin and llvm-dev, I've got a regalloc-related question that you might have an opinion or answer about. In our out-of-tree target we've been doing some bundling before register allocation for quite some time now, and last night a new problem popped up. What the fix should be depends on if this bundle is legal or not: BUNDLE %vreg39<imp-def,dead> *

Hi, For the following test-case: void foo(unsigned, unsigned); void f() { foo(10, 20); foo(10, 20); } clang --target=arm-linux-gnueabi -mthumb -O2 generates: push {r4, r5, r7, lr} movs r4, #10 movs r5, #20 movs r0, r4 movs r1, r5 bl foo movs r0, r4 movs r1, r5 bl foo pop {r4,

...posed to work. I'm running on 2.9. Any comments? @@ -1172,12 +1172,20 @@ bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &MF) { unsigned regASubIdx = mi->getOperand(DstIdx).getSubReg(); TII->reMaterialize(*mbbi, mi, regA, regASubIdx, DefMI, *TRI); ReMatRegs.set(TargetRegisterInfo::virtReg2Index(regB)); ++NumReMats; } else { - BuildMI(*mbbi, mi, mi->getDebugLoc(), TII->get(TargetOpcode::COPY), - regA).addReg(regB); + unsigned regASubIdx = mi->ge...