Displaying 10 results from an estimated 10 matches for "decodestatus".
2013 May 01
0
[LLVMdev] A simpler method to reject undefined encodings
Hi Mihail,
> static DecodeStatus CheckNEONConstraint(const MCInst &Inst, unsigned Insn)
[...]
> ConstraintCheckMethod = "CheckNEONConstraint"
In general I like the idea of an instruction-validation method. I
think it could also potentially solve the SoftFail/UNPREDICTABLE
issues that are looming (and partially re...
2013 Apr 30
3
[LLVMdev] A simpler method to reject undefined encodings
....
This constraint is currently unimplemented and triggers incorrect behaviour
in the MC disassembler. In order to correct this I would have to create
custom decoder methods for a dozen-some instructions which is wasteful. I
would much prefer to be able to define a constraint function like:
static DecodeStatus CheckNEONConstraint(const MCInst &Inst, unsigned Insn)
{
Vd = fieldFromInstruction(Insn, 12, 4);
Vm = fieldFromInstruction(Insn, 0, 4);
Vn = fieldFromInstruction(Insn, 16, 4);
Q = fieldFromInstruction(Insn, 6, 1);
if (Q == 1 && ((Vd & 1) || (Vm & 1) || (Vn & 1)))...
2013 Nov 28
2
[LLVMdev] [llvm] r195903 - AArch64: Fix a bug about disassembling post-index load single element to 4 vectors
...===========================================================================
> --- llvm/trunk/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp (original)
> +++ llvm/trunk/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp Wed Nov 27 19:07:45 2013
> @@ -1342,13 +1342,13 @@ static DecodeStatus DecodeVLDSTLanePostI
> case AArch64::LD4LN_WB_D_fixed: case AArch64::LD4LN_WB_D_register: {
> switch (Opc) {
> case AArch64::LD4LN_WB_B_fixed: case AArch64::LD4LN_WB_B_register:
> - TransferBytes = 3; break;
> + TransferBytes = 4; break;
> case AArc...
2014 Jul 09
2
[LLVMdev] How to resolve decoding conflict?
Hi all,
Short version
I get decoding conflicts during generation of disassembler tables for
my modified PowerPC backend:
001100..........................
................................
ADDIC 001100__________________________
E_LBZ 001100__________________________
Which methods can be used to resolve this kind of error?
Long version:
I'm trying to implement support for the PowerPC
2013 Nov 28
0
[LLVMdev] [llvm] r195903 - AArch64: Fix a bug about disassembling post-index load single element to 4 vectors
...=============================================
>> --- llvm/trunk/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
>> (original)
>> +++ llvm/trunk/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp Wed
>> Nov 27 19:07:45 2013
>> @@ -1342,13 +1342,13 @@ static DecodeStatus DecodeVLDSTLanePostI
>> case AArch64::LD4LN_WB_D_fixed: case AArch64::LD4LN_WB_D_register: {
>> switch (Opc) {
>> case AArch64::LD4LN_WB_B_fixed: case AArch64::LD4LN_WB_B_register:
>> - TransferBytes = 3; break;
>> + TransferBytes = 4; break;...
2013 Nov 28
1
[LLVMdev] [llvm] r195903 - AArch64: Fix a bug about disassembling post-index load single element to 4 vectors
...=========================
>>> --- llvm/trunk/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
>>> (original)
>>> +++ llvm/trunk/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp Wed
>>> Nov 27 19:07:45 2013
>>> @@ -1342,13 +1342,13 @@ static DecodeStatus DecodeVLDSTLanePostI
>>> case AArch64::LD4LN_WB_D_fixed: case AArch64::LD4LN_WB_D_register: {
>>> switch (Opc) {
>>> case AArch64::LD4LN_WB_B_fixed: case AArch64::LD4LN_WB_B_register:
>>> - TransferBytes = 3; break;
>>> + Tra...
2020 Aug 25
3
[TableGen] What to do if there are overlapping instruction patterns?
I've been working on adding support for a (semi-proprietary) extension
for PowerPC called "Paired-Singles". It's a SIMD instruction set
supporting various operations on a vector of 2 32-bit floating point
numbers.
The Extension is found in the PowerPC 750CL, modified variants of it are
used in the Nintendo GameCube (Gekko), the Nintendo Wii (Broadway) and
the Nintendo Wii U
2011 Nov 09
2
[LLVMdev] [cfe-dev] LLVM 3.0rc3 Testing Beginning
...l<llvm::MCParsedAsmOperand*>&)’:
/home/greened/src/llvm-30-rc3/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp:1979:11: warning: variable ‘ExprLoc’ set but not used [-Wunused-but-set-variable]
/home/greened/src/llvm-30-rc3/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp: In function ‘DecodeStatus DecodeCopMemInstruction(llvm::MCInst&, unsigned int, uint64_t, const void*)’:
/home/greened/src/llvm-30-rc3/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp:1241:12: warning: variable ‘idx_mode’ set but not used [-Wunused-but-set-variable]
/home/greened/src/llvm-30-rc3/clang-3.0rc3.src/lib...
2011 Nov 08
0
[LLVMdev] [cfe-dev] LLVM 3.0rc3 Testing Beginning
On 7 November 2011 22:00, Bill Wendling <wendling at apple.com> wrote:
> We are starting on our third (and hopefully last) round of testing for LLVM 3.0. Please visit:
>
> http://llvm.org/pre-releases/3.0/rc3/
>
> for the sources. There are also binaries for Darwin up there, with more to come during the week. Please build this release candidate, test it out on your
2011 Nov 07
6
[LLVMdev] LLVM 3.0rc3 Testing Beginning
Good day, LLVMers!
We are starting on our third (and hopefully last) round of testing for LLVM 3.0. Please visit:
http://llvm.org/pre-releases/3.0/rc3/
for the sources. There are also binaries for Darwin up there, with more to come during the week. Please build this release candidate, test it out on your projects, and let us know if you find any regressions from the 2.9 release.
Please keep