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...are fixed and using the a custom DecoderMethod for the rest). With this change I can disassemble INITSP_2r instructions but it breaks the decoding of ADD_3r instructions. Consider the following bit pattern: 0001000000000000 This is an ADD_3r instruction. Before adding INITSP_2r the autogenerated decodeInstruction method would identify this as a possible ADD_3r instruction and it would call the associated decoder method (Decode3RInstruction) which returns Success. After adding INITSP_2r the autogenerated decodeInstruction method identifies this as a possible INITSP_2r instruction and it calls the associat...

...the a custom DecoderMethod for the rest). With this change I can disassemble INITSP_2r instructions but it breaks the decoding of ADD_3r instructions. Consider the following bit pattern: > > 0001000000000000 > > This is an ADD_3r instruction. Before adding INITSP_2r the autogenerated decodeInstruction method would identify this as a possible ADD_3r instruction and it would call the associated decoder method (Decode3RInstruction) which returns Success. After adding INITSP_2r the autogenerated decodeInstruction method identifies this as a possible INITSP_2r instruction and it calls the associat...

Hello Daniel, At the moment we are preparing the patch for disassembling microMIPS 16 bit instructions and it will be on Phabricator tomorrow or on Wednesday. Functionality is implemented in MipsDisassembler::getInstruction where first two bytes are read and decodeInstruction is called with DecoderTableMicroMips16 and only if it fails we read 4 bytes and call decodeInstruction with DecoderTableMicroMips32. Regards, Zoran ________________________________ From: Daniel Sanders Sent: Sunday, November 02, 2014 5:49 PM To: Jun Koi; Vladimir Medic; Sasa Stankovic; Jozef...

Hi all, Short version I get decoding conflicts during generation of disassembler tables for my modified PowerPC backend: 001100.......................... ................................ ADDIC 001100__________________________ E_LBZ 001100__________________________ Which methods can be used to resolve this kind of error? Long version: I'm trying to implement support for the PowerPC

Hi, We have this line in micromips-16-bit-instructions.s # CHECK-EB: addu16 $6, $17, $4 # encoding: [0x07,0x42] However, when I check this with llvm-mc, like below, I dont get back the assembly. This is against the latest LLVM code. What is wrong here? Thanks, Jun $ echo "0x07,0x42"|./Release+Asserts/bin/llvm-mc -disassemble -triple=mips -show-encoding -mattr=micromips

I've been working on adding support for a (semi-proprietary) extension for PowerPC called "Paired-Singles". It's a SIMD instruction set supporting various operations on a vector of 2 32-bit floating point numbers. The Extension is found in the PowerPC 750CL, modified variants of it are used in the Nintendo GameCube (Gekko), the Nintendo Wii (Broadway) and the Nintendo Wii U