search for: dagtodag

Is it possible to get a register number to which the value is allocated to in MIPS in DAGToDAG class? More Specifically: SDValue Reg3 = Node->getOperand(3); if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(Reg3)) { op3 = cast<RegisterSDNode>(Reg3)->getReg(); fprintf(...

> On Feb 27, 2015, at 1:59 AM, Ambuj Agrawal <ambujbwt at gmail.com> wrote: > > Is it possible to get a register number to which the value is allocated to in MIPS in DAGToDAG class? > > More Specifically: > SDValue Reg3 = Node->getOperand(3); > if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(Reg3)) > { > op3 = cast<RegisterSDNode>(Reg3)->getReg();...

...buj On Fri, Feb 27, 2015 at 5:46 PM, Quentin Colombet <qcolombet at apple.com> wrote: > > > On Feb 27, 2015, at 1:59 AM, Ambuj Agrawal <ambujbwt at gmail.com> wrote: > > > > Is it possible to get a register number to which the value is allocated > to in MIPS in DAGToDAG class? > > > > More Specifically: > > SDValue Reg3 = Node->getOperand(3); > > if (RegisterSDNode *R = > dyn_cast<RegisterSDNode>(Reg3)) > > { > > op3 = cast<Registe...

...e anything to do with > instruction selection [any more?]). However, the inconsistent > filenames are a > bit confusing. Perhaps somebody should rename the lot of them? Sure, I'd support renaming them to <target>TargetLowering.cpp etc. > The same goes for <Target>ISelDAGToDAG.cpp, which defines a class > called > <Target>DAGToDAGISel. The DAGToDAG suffix is actually a pretty old historical artifact at this point. It would be better to rename the classes and files to <target>DAGISel. -Chris

...renamed at some time (which makes sense, since I don't think that the TargetLowering classes have anything to do with instruction selection [any more?]). However, the inconsistent filenames are a bit confusing. Perhaps somebody should rename the lot of them? The same goes for <Target>ISelDAGToDAG.cpp, which defines a class called <Target>DAGToDAGISel. Gr. Matthijs -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 189 bytes Desc: Digital signature URL: <http://lists.llvm.org/pipermail/llvm-dev/at...

Ok, I understand a bit more of what's going on in my phi example. Coming into DAGtoDAG we have this code: bb74: x = phi(1.0:bb134, %r1450:bb108) y = phi(undef:bb134, x:bb108) [...] bb108: %r1450 = <expr> After DAGtoDAG we have: bb134: %reg1459 = IMPLICIT_DEF %reg1458 = 1.0 bb74: %reg1176 = phi(%reg1458:bb134, %reg1253:bb108) %reg1177 = phi(%reg1459:bb134, %re...

On Mon, Jun 30, 2014 at 02:40:43AM -0700, Quentin Colombet wrote: > Hi Arsen, > > > > On Jun 19, 2014, at 10:43 PM, Arsen Hakobyan <artinetstudio at gmail.com> wrote: > > > > Hi all, > > > > I want to generate an assembly instruction for my target using target > > description representation of the instruction. The problem is that I want to

No objections from me to make it run later. I didn't see the potential conflicts when I added that code. Delayed combine, custom lowering, or DAGToDAGISel all seem like viable options to me. On Mon, Aug 26, 2019 at 2:04 PM Roman Lebedev <lebedev.ri at gmail.com> wrote: > I have previously posted these two patches: > > [X86][CodeGen][NFC] Delay `combineIncDecVector()` from DAGCombine to > X86DAGToDAGISel > https://reviews.ll...

I think DAGToDAG is too late because the build_vector has already been turned into a constant pool load by then so it’s a little difficult to get back. Maybe we can delay it to !DCI.isBeforeLegalizeOps()? That would at least let the first DAG combine and the post type legalization DAG combine see the add, 1. +Sanj...

Hi all, As you knwo already, I'm trying to change DAGCombiner so that it process the nodes in topological order. Doing so is not difficult per se, but this creates various improvements and regression to the existing test suite. I'd like to work through as many of the regressions as possible ahead of time. One source of such regressions is combineIncDecVector in the X86 backend. It

..."prefix $i1 body $r0, $r1, $i2", [(... some pattern here)]>; In Insn pattern whole string goes to AsmString property. How can I do it with tablegen? Any examples from existing backends? P.S. Of course I can do custom node with one more parameter and write pattern matching in DAGToDAG selection, etc. I just wonder: may be there is some surprising tablegen magic to do it quickly in-place? In GCC md patterns allows C-code snippets for such cases, but in LLVM I can not find such possibility. --- With best regards, Konstnatin

...ad branch extension can be combined with MVE to generate vectorized loops in which the epilogue is executed within the predicated vector body. The proposal is for this to be supported through a series of pass: 1) IR LoopPass to identify suitable loops and insert the intrinsics proposed above. 2) DAGToDAG ISel which makes the intrinsics, almost 1-1, to a pseduo instruction. 3) A final MachineFunctionPass to expand the pseudo instructions. To help / enable the lowering of of an i1 vector, the VPR register has been added. This is a status register that contains the P0 predicate and is also used to...

Jim, > The an instruction that uses R0 and R1 as fixed input registers and R2 for output could define itself using those register classs: > def myInst : baseclass<…, (outs GPRr2:$dst), (ins GPRr0:$src1, GPRr1:$src2), …> > Use those reg classes in pattern to match also, and things should just work. The register allocator can take care of any reg-to-reg copies that are required. As

On May 9, 2012, at 4:27 AM, Anton Korobeynikov wrote: > Hello Jonas, > >> I wonder, what would be the best solution for instructions that require >> operands in a particular register, and even gives the result in a particular >> register? > You need to custom select such instruction. See e.g. div / idiv on x86 > as an example. That's often easiest, yes;