Displaying 7 results from an estimated 7 matches for "dagcombinerinfo".
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dagcombineinfo
2007 Aug 08
2
[LLVMdev] Destination register needs to be valid after callee saved register restore when tail calling
Hello, Arnold.
> with the sentence i tried to express the question whether there is a
> way to persuade the code generator to use another register to load (or
> move) the function pointer to (right before the callee saved register
> restore) but thinking a little further that's nonsense.
Why don't define some special op for callee address and custom lower it?
I really
2012 Aug 01
0
[LLVMdev] X86 isTargetShuffle Question
...element load.
/// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
/// shuffles have been customed lowered so we need to handle those here.
static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
TargetLowering::DAGCombinerInfo &DCI) {
[...]
if (!isTargetShuffle(InVec.getOpcode()))
return SDValue();
[...]
}
It seems like we'd want to be able to "find scalars" or fold loads in as
many different kinds of shuffle as possible. But a whole bunch went
missing between 2.9 and 3.1, particularly AVX shuff...
2007 Aug 08
1
[LLVMdev] Destination register needs to be valid after callee saved register restore when tail calling
...cases (modulo many unknown
bugs :) where the tail called function is a destination within the
source file and frame pointer elimination is performed. i implemented
it as a dagcombiner transformation running in post legalized phase
within the X86TargetLowering::PerformDAGCombine(SDNode *N,
DAGCombinerInfo &DCI). now to my problem:
When tail calling a function pointer the register the function
pointer was loaded to might be invalidated by the restored callee
saved registers.
...
movl 12(%esp), %esi << 12(%esp) contains the function pointer
movl %eax, 44(%esp)
movl 32(%esp),...
2015 Jul 10
3
[LLVMdev] Why change "sub x, 5" to "add x, -5" ?
2015-07-08 17:58 GMT+02:00 escha <escha at apple.com>:
> [...]
>
> If you want to “revert" this sort of thing, you can do it at Select() time
> or PreprocessISelDAG(), which is what I did on an out-of-tree backend to
> turn add X, -C into sub X, C on selection time. This still lets all the
> intermediate optimizations take advantage of the canonicalization.
>
>
2009 May 21
0
[LLVMdev] [PATCH] Add new phase to legalization to handle vector operations
On Wed, May 20, 2009 at 4:55 PM, Dan Gohman <gohman at apple.com> wrote:
> Can you explain why you chose the approach of using a new pass?
> I pictured removing LegalizeDAG's type legalization code would
> mostly consist of finding all the places that use TLI.getTypeAction
> and just deleting code for handling its Expand and Promote. Are you
> anticipating something more
2009 May 20
2
[LLVMdev] [PATCH] Add new phase to legalization to handle vector operations
On May 20, 2009, at 1:34 PM, Eli Friedman wrote:
> On Wed, May 20, 2009 at 1:19 PM, Eli Friedman
> <eli.friedman at gmail.com> wrote:
>
>> Per subject, this patch adding an additional pass to handle vector
>>
>> operations; the idea is that this allows removing the code from
>>
>> LegalizeDAG that handles illegal types, which should be a significant
2009 May 21
2
[LLVMdev] [PATCH] Add new phase to legalization to handle vector operations
...// Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands
- // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2;
-
- // NOTE: on targets without efficient SELECT of bools, we can always use
- // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
- TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, NULL);
- Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSLo.getValueType()),
- LHSLo, RHSLo, LowCC, false, DagCombineInfo, dl);
- if (!Tmp1.getNode())
- Tmp1 = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSLo.getValueTy...