Displaying 7 results from an estimated 7 matches for "dagcombineinfo".
2013 Jul 01
3
[LLVMdev] Advices Required: Best practice to share logic between DAG combine and target lowering?
...t sequences into a ARMISD::build_vector, I still need to know if it would be profitable, i.e., if DAGCombine will remove the bitcasts that combining/lowering is about to insert.
Since target specific DAGCombine are also done in TargetLowering I do not have access to more DAGCombine logic (at least DAGCombineInfo is not providing the require information).
What did I miss?
Thanks,
-Quentin
>
> -Eli
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2013 Jul 01
0
[LLVMdev] Advices Required: Best practice to share logic between DAG combine and target lowering?
...D::build_vector, I still need to know if it would be
> profitable, i.e., if DAGCombine will remove the bitcasts that
> combining/lowering is about to insert.
>
> Since target specific DAGCombine are also done in TargetLowering I do not
> have access to more DAGCombine logic (at least DAGCombineInfo is not
> providing the require information).
>
> What did I miss?
>
>
Err, wait, sorry, my fault; I missed that you only insert the bitcasts on
the other side of the branch.
You should be able to do it the other way, though: generate the
build_vector unconditionally, and pull insert...
2013 Jul 01
0
[LLVMdev] Advices Required: Best practice to share logic between DAG combine and target lowering?
On Mon, Jul 1, 2013 at 11:30 AM, Quentin Colombet <qcolombet at apple.com>wrote:
> Hi,
>
> ** Problematic **
> I am looking for advices to share some logic between DAG combine and
> target lowering.
>
> Basically, I need to know if a bitcast that is about to be inserted during
> target specific isel lowering will be eliminated during DAG combine.
>
> Let me
2013 Jul 01
3
[LLVMdev] Advices Required: Best practice to share logic between DAG combine and target lowering?
Hi,
** Problematic **
I am looking for advices to share some logic between DAG combine and target lowering.
Basically, I need to know if a bitcast that is about to be inserted during target specific isel lowering will be eliminated during DAG combine.
Let me know if there is another, better supported, approach for this kind of problems.
** Motivating Example **
The motivating example comes
2009 May 21
0
[LLVMdev] [PATCH] Add new phase to legalization to handle vector operations
On Wed, May 20, 2009 at 4:55 PM, Dan Gohman <gohman at apple.com> wrote:
> Can you explain why you chose the approach of using a new pass?
> I pictured removing LegalizeDAG's type legalization code would
> mostly consist of finding all the places that use TLI.getTypeAction
> and just deleting code for handling its Expand and Promote. Are you
> anticipating something more
2009 May 20
2
[LLVMdev] [PATCH] Add new phase to legalization to handle vector operations
On May 20, 2009, at 1:34 PM, Eli Friedman wrote:
> On Wed, May 20, 2009 at 1:19 PM, Eli Friedman
> <eli.friedman at gmail.com> wrote:
>
>> Per subject, this patch adding an additional pass to handle vector
>>
>> operations; the idea is that this allows removing the code from
>>
>> LegalizeDAG that handles illegal types, which should be a significant
2009 May 21
2
[LLVMdev] [PATCH] Add new phase to legalization to handle vector operations
...op1) < hi(op2) // Signedness depends on operands
- // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2;
-
- // NOTE: on targets without efficient SELECT of bools, we can always use
- // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
- TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, NULL);
- Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSLo.getValueType()),
- LHSLo, RHSLo, LowCC, false, DagCombineInfo, dl);
- if (!Tmp1.getNode())
- Tmp1 = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSLo.getValueType()),
-...