search for: daddiu

...2 .globl main .set nomips16 .set nomicromips .ent main .type main, @function main: .frame $fp,48,$31 # vars= 16, regs= 3/0, args= 0, gp= 0 .mask 0xd0000000,-8 .fmask 0x00000000,0 .set noreorder .set nomacro daddiu $sp,$sp,-48 gssq $31,$fp,32($sp) sd $28,24($sp) move $fp,$sp lui $28,%hi(%neg(%gp_rel(main))) daddu $28,$28,$25 daddiu $28,$28,%lo(%neg(%gp_rel(main))) move $2,$4 sd $5,8($fp) sll $2,$2,0 sw $2,0($fp) ld $2,%...

...;> .ent main >> .type main, @function >> main: >> .frame $fp,48,$31 # vars= 16, regs= 3/0, args= 0, gp= 0 >> .mask 0xd0000000,-8 >> .fmask 0x00000000,0 >> .set noreorder >> .set nomacro >> daddiu $sp,$sp,-48 >> gssq $31,$fp,32($sp) >> sd $28,24($sp) >> move $fp,$sp >> lui $28,%hi(%neg(%gp_rel(main))) >> daddu $28,$28,$25 >> daddiu $28,$28,%lo(%neg(%gp_rel(main))) >> move $2,$4 >> sd $5...

...zero # Crash if we return END(__start) diff --git a/usr/klibc/arch/mips64/crt0.S b/usr/klibc/arch/mips64/crt0.S index 775a919..3f1c2a9 100644 --- a/usr/klibc/arch/mips64/crt0.S +++ b/usr/klibc/arch/mips64/crt0.S @@ -10,22 +10,12 @@ #include <machine/asm.h> -NESTED(__start, 64, sp) - daddiu sp,sp,-64 - sd zero, 32(sp) - - # Initialize gp - lui gp,%highest(_gp) # load highest "halfword" - daddiu gp,gp,%higher(_gp) # merge next "halfword" - dsll gp,gp,16 # shift by one halfword - daddiu gp,gp,%hi(_gp) # merge next "halfword" - dsll gp,gp,16...

...ch/mips64/crt0.S @@ -0,0 +1,31 @@ +# +# arch/mips64/crt0.S +# +# Does arch-specific initialization and invokes __libc_init +# with the appropriate arguments. +# +# See __static_init.c or __shared_init.c for the expected +# arguments. +# + +#include <machine/asm.h> + +NESTED(__start, 64, sp) + daddiu sp,sp,-64 + sd zero, 32(sp) + + # Initialize gp + lui gp,%highest(_gp) # load highest "halfword" + daddiu gp,gp,%higher(_gp) # merge next "halfword" + dsll gp,gp,16 # shift by one halfword + daddiu gp,gp,%hi(_gp) # merge next "halfword" + dsll gp,gp,16...

Hi, I noticed that klibc started crashing on 64-bit MIPS and in my quest to fix the bug I got a bit carried away and fixed a few other things as well. Here are various miscellaneous MIPS patches, although the first patch is the important one. Thanks, James *** BLURB HERE *** James Cowgill (5): mips64: compile with -mno-abicalls mips: use -Ttext-segment when linking shared library

Has anyone experimented with generating non-PIC for MIPS64 and the n64 ABI? Currently MipsISelLowering.cpp uses conditions like: if ((getTargetMachine().getRelocationModel() == Reloc::PIC_) || IsN64) { } around any PIC code generation. Is generating non-PIC just untested, or is it known not to work? I can't find any discussion of it anywhere. I ran into this when trying to see why

...) > > dsll $1, $1, 32 > > lui $2, %hi(foo) > > add $2, $2, %lo(foo) > > add $1, $1, $2 > > which is 6 instructions per-symbol referenced. The current PIC > implementation generates this: > > lui $1, %hi(%neg(%gp_rel(bar))) > > daddu $1, $1, $25 > > daddiu $1, $1, %lo(%neg(%gp_rel(bar))) > > ld $2, %got_disp(foo)($1) > > which is a one-time cost of 3 instructions to set up the GOT pointer, plus > one load per-symbol referenced. > > > > *From:* llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] *On > B...

On 10 May 2014, at 13:53, Tim Northover <t.p.northover at gmail.com> wrote: > It doesn't make sense for everything though, particularly if you want > target-specific IR to simply not exist. What would you map ARM's > "ldrex" to on x86? This isn't a great example. Having load-linked / store-conditional in the IR would make a number of transforms related to

Hello everyone, in http://reviews.llvm.org/D7696 bhushan added a mips64 UnwindAssembly plugin (a plugin that looks at assembly code to find out how to unwind the stack frame). Since I was about to write such a plugin (though for mips32) myself, I used it as a starting point for a slightly different implementation [1], replacing hard coded instruction encodings by calls to the LLVM disassembler.