Displaying 2 results from an estimated 2 matches for "d6f46ae0".
2012 Aug 14
0
[LLVMdev] x86 REP-prefixed instructions seem to be dropped by instruction decoder?
On 13 August 2012 12:02, Andrew Ruef <awruef at umd.edu> wrote:
> I think there's a bug somewhere in TableGen for the X86 disassembler
> emitter. The following test:
>
> $ echo "0xF3 0xA5" | ./bin/llvm-mc -disassemble
> .section __TEXT,__text,regular,pure_instructions
> movsd
>
> (from llvm trunk)
>
> 0xF3 is the REP prefix, so the
2012 Aug 13
2
[LLVMdev] x86 REP-prefixed instructions seem to be dropped by instruction decoder?
I think there's a bug somewhere in TableGen for the X86 disassembler
emitter. The following test:
$ echo "0xF3 0xA5" | ./bin/llvm-mc -disassemble
.section __TEXT,__text,regular,pure_instructions
movsd
(from llvm trunk)
0xF3 is the REP prefix, so the printed instruction should be 'rep
movsd', however all that is printed is 'movsd'. It seems that there