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...ich I plan to use exclusively a scalable vector type like <vscale x 4 x i16>. > > > I applied the 3 patches discussed in http://lists.llvm.org/pipermail/llvm-dev/2019-March/130852.html (https://reviews.llvm.org/D32530, https://reviews.llvm.org /D47770, and https://reviews.llvm.org/D53137). > However, it seems there are quite a few features missing from this patch to add good scalable vector support in LLVM. For example the patches do not parse the stepvector. > So I had to get inspired from the lib/AsmParser and lib/IR folders from https://github.com/ARM-software/LLVM-S...

...e a "new IR", so it needs to be a change that everyone is conscious and willing to take on the project to stabilize it until the next release. Here are some of the reviews on the matter, mostly agreed upon by the current reviewers: https://reviews.llvm.org/D32530 https://reviews.llvm.org/D53137 https://reviews.llvm.org/D47770 And the corresponding RFC threads: http://lists.llvm.org/pipermail/llvm-dev/2016-November/106819.html http://lists.llvm.org/pipermail/llvm-dev/2017-March/110772.html http://lists.llvm.org/pipermail/llvm-dev/2017-June/113587.html http://lists.llvm.org/pipermail/llvm-...

I had a phone conversation yesterday with Graham, Francesco, and Kristof. There is one more reason to go with the native type change: ARM has already written the code with the SV types, and they have patches ready to be reviewed and integrated in LLVM. As I don't want to stand in the way of getting SVE in LLVM as soon as possible, I will also support the integration of the existing patches

Hi Graham, Thanks for your kind explanation. There was internal discussion about it. If possible, can you let me know the Clang/LLVM CodeGen patches for the vector type on phabricator please? I would like to check what kinds of the restrictions the type causes on Clang/LLVM. Thanks, JinGu Kang ________________________________ From: Graham Hunter <Graham.Hunter at arm.com> Sent: 28 May