search for: d47780

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[RFC][SVE] Supporting SIMD instruction sets with variable vector lengths
2019 May 24
2
[RFC][SVE] Supporting SIMD instruction sets with variable vector lengths
...reviews.llvm.org/D47776 > 11. Initial addition patterns: https://reviews.llvm.org/D47777 > 12. Initial left-shift patterns: https://reviews.llvm.org/D47778 > 13. Implement copy logic for Z regs: https://reviews.llvm.org/D47779 > 14. Prevectorized loop unit test: https://reviews.llvm.org/D47780 > > _______________________________________________ > LLVM Developers mailing list > llvm-dev at lists.llvm.org > http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev > _______________________________________________ > LLVM Developers mailing list > llvm-dev at lists.llvm...
[RFC][SVE] Supporting SIMD instruction sets with variable vector lengths
2018 Jul 30
5
[RFC][SVE] Supporting SIMD instruction sets with variable vector lengths
...reviews.llvm.org/D47776 > 11. Initial addition patterns: https://reviews.llvm.org/D47777 > 12. Initial left-shift patterns: https://reviews.llvm.org/D47778 > 13. Implement copy logic for Z regs: https://reviews.llvm.org/D47779 > 14. Prevectorized loop unit test: https://reviews.llvm.org/D47780 >
[RFC][SVE] Supporting SIMD instruction sets with variable vector lengths
2018 Jun 05
14
[RFC][SVE] Supporting SIMD instruction sets with variable vector lengths
...e patterns: https://reviews.llvm.org/D47776 11. Initial addition patterns: https://reviews.llvm.org/D47777 12. Initial left-shift patterns: https://reviews.llvm.org/D47778 13. Implement copy logic for Z regs: https://reviews.llvm.org/D47779 14. Prevectorized loop unit test: https://reviews.llvm.org/D47780
[EXT] Re: [RFC][SVE] Supporting SIMD instruction sets with variable vector lengths
2019 May 24
2
[EXT] Re: [RFC][SVE] Supporting SIMD instruction sets with variable vector lengths
...e patterns: https://reviews.llvm.org/D47776 11. Initial addition patterns: https://reviews.llvm.org/D47777 12. Initial left-shift patterns: https://reviews.llvm.org/D47778 13. Implement copy logic for Z regs: https://reviews.llvm.org/D47779 14. Prevectorized loop unit test: https://reviews.llvm.org/D47780 _______________________________________________ LLVM Developers mailing list llvm-dev at lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/2...
[EXT] Re: [RFC][SVE] Supporting SIMD instruction sets with variable vector lengths
2019 May 27
2
[EXT] Re: [RFC][SVE] Supporting SIMD instruction sets with variable vector lengths
...e patterns: https://reviews.llvm.org/D47776 11. Initial addition patterns: https://reviews.llvm.org/D47777 12. Initial left-shift patterns: https://reviews.llvm.org/D47778 13. Implement copy logic for Z regs: https://reviews.llvm.org/D47779 14. Prevectorized loop unit test: https://reviews.llvm.org/D47780 _______________________________________________ LLVM Developers mailing list llvm-dev at lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/2...
[EXT] Re: [RFC][SVE] Supporting SIMD instruction sets with variable vector lengths
2019 Jun 03
2
[EXT] Re: [RFC][SVE] Supporting SIMD instruction sets with variable vector lengths
...reviews.llvm.org/D47776 > 11. Initial addition patterns: https://reviews.llvm.org/D47777 > 12. Initial left-shift patterns: https://reviews.llvm.org/D47778 > 13. Implement copy logic for Z regs: https://reviews.llvm.org/D47779 > 14. Prevectorized loop unit test: https://reviews.llvm.org/D47780 > > _______________________________________________ > LLVM Developers mailing list > llvm-dev at lists.llvm.org > http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/piperma...
[RFC][SVE] Supporting SIMD instruction sets with variable vector lengths
2018 Jul 30
7
[RFC][SVE] Supporting SIMD instruction sets with variable vector lengths
...; 11. Initial addition patterns: https://reviews.llvm.org/D47777 > > 12. Initial left-shift patterns: https://reviews.llvm.org/D47778 > > 13. Implement copy logic for Z regs: https://reviews.llvm.org/D47779 > > 14. Prevectorized loop unit test: https://reviews.llvm.org/D47780 > > > -- Hal Finkel Lead, Compiler Technology and Programming Languages Leadership Computing Facility Argonne National Laboratory -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20180730/25c38df...
[RFC][SVE] Supporting SIMD instruction sets with variable vector lengths
2018 Jul 02
3
[RFC][SVE] Supporting SIMD instruction sets with variable vector lengths
...reviews.llvm.org/D47776 > 11. Initial addition patterns: https://reviews.llvm.org/D47777 > 12. Initial left-shift patterns: https://reviews.llvm.org/D47778 > 13. Implement copy logic for Z regs: https://reviews.llvm.org/D47779 > 14. Prevectorized loop unit test: https://reviews.llvm.org/D47780 > > _______________________________________________ > LLVM Developers mailing list > llvm-dev at lists.llvm.org > http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev -- Simon Moll Researcher / PhD Student Compiler Design Lab (Prof. Hack) Saarland University, Computer Science...