search for: d47776

Displaying 8 results from an estimated 8 matches for "d47776".

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[RFC][SVE] Supporting SIMD instruction sets with variable vector lengths
2019 May 24
2
[RFC][SVE] Supporting SIMD instruction sets with variable vector lengths
...ering cleanup: https://reviews.llvm.org/D47772 > 7. Add VScale intrinsic: https://reviews.llvm.org/D47773 > 8. Add StepVector intrinsic: https://reviews.llvm.org/D47774 > 9. Add SplatVector intrinsic: https://reviews.llvm.org/D47775 > 10. Initial store patterns: https://reviews.llvm.org/D47776 > 11. Initial addition patterns: https://reviews.llvm.org/D47777 > 12. Initial left-shift patterns: https://reviews.llvm.org/D47778 > 13. Implement copy logic for Z regs: https://reviews.llvm.org/D47779 > 14. Prevectorized loop unit test: https://reviews.llvm.org/D47780 > > ______...
[RFC][SVE] Supporting SIMD instruction sets with variable vector lengths
2018 Jul 30
5
[RFC][SVE] Supporting SIMD instruction sets with variable vector lengths
...ering cleanup: https://reviews.llvm.org/D47772 > 7. Add VScale intrinsic: https://reviews.llvm.org/D47773 > 8. Add StepVector intrinsic: https://reviews.llvm.org/D47774 > 9. Add SplatVector intrinsic: https://reviews.llvm.org/D47775 > 10. Initial store patterns: https://reviews.llvm.org/D47776 > 11. Initial addition patterns: https://reviews.llvm.org/D47777 > 12. Initial left-shift patterns: https://reviews.llvm.org/D47778 > 13. Implement copy logic for Z regs: https://reviews.llvm.org/D47779 > 14. Prevectorized loop unit test: https://reviews.llvm.org/D47780 >
[RFC][SVE] Supporting SIMD instruction sets with variable vector lengths
2018 Jun 05
14
[RFC][SVE] Supporting SIMD instruction sets with variable vector lengths
...771 6. Intrinsic lowering cleanup: https://reviews.llvm.org/D47772 7. Add VScale intrinsic: https://reviews.llvm.org/D47773 8. Add StepVector intrinsic: https://reviews.llvm.org/D47774 9. Add SplatVector intrinsic: https://reviews.llvm.org/D47775 10. Initial store patterns: https://reviews.llvm.org/D47776 11. Initial addition patterns: https://reviews.llvm.org/D47777 12. Initial left-shift patterns: https://reviews.llvm.org/D47778 13. Implement copy logic for Z regs: https://reviews.llvm.org/D47779 14. Prevectorized loop unit test: https://reviews.llvm.org/D47780
[EXT] Re: [RFC][SVE] Supporting SIMD instruction sets with variable vector lengths
2019 May 24
2
[EXT] Re: [RFC][SVE] Supporting SIMD instruction sets with variable vector lengths
...771 6. Intrinsic lowering cleanup: https://reviews.llvm.org/D47772 7. Add VScale intrinsic: https://reviews.llvm.org/D47773 8. Add StepVector intrinsic: https://reviews.llvm.org/D47774 9. Add SplatVector intrinsic: https://reviews.llvm.org/D47775 10. Initial store patterns: https://reviews.llvm.org/D47776 11. Initial addition patterns: https://reviews.llvm.org/D47777 12. Initial left-shift patterns: https://reviews.llvm.org/D47778 13. Implement copy logic for Z regs: https://reviews.llvm.org/D47779 14. Prevectorized loop unit test: https://reviews.llvm.org/D47780 ___________________________________...
[EXT] Re: [RFC][SVE] Supporting SIMD instruction sets with variable vector lengths
2019 May 27
2
[EXT] Re: [RFC][SVE] Supporting SIMD instruction sets with variable vector lengths
...771 6. Intrinsic lowering cleanup: https://reviews.llvm.org/D47772 7. Add VScale intrinsic: https://reviews.llvm.org/D47773 8. Add StepVector intrinsic: https://reviews.llvm.org/D47774 9. Add SplatVector intrinsic: https://reviews.llvm.org/D47775 10. Initial store patterns: https://reviews.llvm.org/D47776 11. Initial addition patterns: https://reviews.llvm.org/D47777 12. Initial left-shift patterns: https://reviews.llvm.org/D47778 13. Implement copy logic for Z regs: https://reviews.llvm.org/D47779 14. Prevectorized loop unit test: https://reviews.llvm.org/D47780 ___________________________________...
[EXT] Re: [RFC][SVE] Supporting SIMD instruction sets with variable vector lengths
2019 Jun 03
2
[EXT] Re: [RFC][SVE] Supporting SIMD instruction sets with variable vector lengths
...ering cleanup: https://reviews.llvm.org/D47772 > 7. Add VScale intrinsic: https://reviews.llvm.org/D47773 > 8. Add StepVector intrinsic: https://reviews.llvm.org/D47774 > 9. Add SplatVector intrinsic: https://reviews.llvm.org/D47775 > 10. Initial store patterns: https://reviews.llvm.org/D47776 > 11. Initial addition patterns: https://reviews.llvm.org/D47777 > 12. Initial left-shift patterns: https://reviews.llvm.org/D47778 > 13. Implement copy logic for Z regs: https://reviews.llvm.org/D47779 > 14. Prevectorized loop unit test: https://reviews.llvm.org/D47780 > > ______...
[RFC][SVE] Supporting SIMD instruction sets with variable vector lengths
2018 Jul 30
7
[RFC][SVE] Supporting SIMD instruction sets with variable vector lengths
...org/D47772 > > 7. Add VScale intrinsic: https://reviews.llvm.org/D47773 > > 8. Add StepVector intrinsic: https://reviews.llvm.org/D47774 > > 9. Add SplatVector intrinsic: https://reviews.llvm.org/D47775 > > 10. Initial store patterns: https://reviews.llvm.org/D47776 > > 11. Initial addition patterns: https://reviews.llvm.org/D47777 > > 12. Initial left-shift patterns: https://reviews.llvm.org/D47778 > > 13. Implement copy logic for Z regs: https://reviews.llvm.org/D47779 > > 14. Prevectorized loop unit test: https://revi...
[RFC][SVE] Supporting SIMD instruction sets with variable vector lengths
2018 Jul 02
3
[RFC][SVE] Supporting SIMD instruction sets with variable vector lengths
...ering cleanup: https://reviews.llvm.org/D47772 > 7. Add VScale intrinsic: https://reviews.llvm.org/D47773 > 8. Add StepVector intrinsic: https://reviews.llvm.org/D47774 > 9. Add SplatVector intrinsic: https://reviews.llvm.org/D47775 > 10. Initial store patterns: https://reviews.llvm.org/D47776 > 11. Initial addition patterns: https://reviews.llvm.org/D47777 > 12. Initial left-shift patterns: https://reviews.llvm.org/D47778 > 13. Implement copy logic for Z regs: https://reviews.llvm.org/D47779 > 14. Prevectorized loop unit test: https://reviews.llvm.org/D47780 > > ______...