search for: d32530

Displaying 12 results from an estimated 12 matches for "d32530".

2019 Jul 16
4
Scalable Vector Types in IR - Next Steps?
...> - then generate assembly code for my Connex back end, which I plan to use exclusively a scalable vector type like <vscale x 4 x i16>. > > > I applied the 3 patches discussed in http://lists.llvm.org/pipermail/llvm-dev/2019-March/130852.html (https://reviews.llvm.org/D32530, https://reviews.llvm.org /D47770, and https://reviews.llvm.org/D53137). > However, it seems there are quite a few features missing from this patch to add good scalable vector support in LLVM. For example the patches do not parse the stepvector. > So I had to get inspired from the lib/A...
2019 Mar 08
2
Scalable Vector Types in IR - Next Steps?
...anager", we can't create a "new IR", so it needs to be a change that everyone is conscious and willing to take on the project to stabilize it until the next release. Here are some of the reviews on the matter, mostly agreed upon by the current reviewers: https://reviews.llvm.org/D32530 https://reviews.llvm.org/D53137 https://reviews.llvm.org/D47770 And the corresponding RFC threads: http://lists.llvm.org/pipermail/llvm-dev/2016-November/106819.html http://lists.llvm.org/pipermail/llvm-dev/2017-March/110772.html http://lists.llvm.org/pipermail/llvm-dev/2017-June/113587.html http:...
2019 Mar 29
2
Scalable Vector Types in IR - Next Steps?
I had a phone conversation yesterday with Graham, Francesco, and Kristof. There is one more reason to go with the native type change: ARM has already written the code with the SV types, and they have patches ready to be reviewed and integrated in LLVM. As I don't want to stand in the way of getting SVE in LLVM as soon as possible, I will also support the integration of the existing patches
2019 Jun 03
2
[EXT] Re: [RFC][SVE] Supporting SIMD instruction sets with variable vector lengths
...i64 %index, mul (i64 %vscale64, i64 4) > %4 = icmp eq i64 %index.next, %n.vec > br i1 %4, label %middle.block, label %vector.body, !llvm.loop !5 > `` > > ========== > 7. Patches > ========== > > List of patches: > > 1. Extend VectorType: https://reviews.llvm.org/D32530 > 2. Vector element type Tablegen constraint: https://reviews.llvm.org/D47768 > 3. LLT support for scalable vectors: https://reviews.llvm.org/D47769 > 4. EVT strings and Type mapping: https://reviews.llvm.org/D47770 > 5. SVE Calling Convention: https://reviews.llvm.org/D47771 > 6. In...
2019 Mar 15
5
Scalable Vector Types in IR - Next Steps?
On 3/15/19 10:58 AM, David Greene wrote: > Renato Golin <rengolin at gmail.com> writes: > >> On Fri, 15 Mar 2019 at 15:30, Finkel, Hal J. via llvm-dev >> <llvm-dev at lists.llvm.org> wrote: >>> I've talked with a number of people about this as well, and I think that >>> I understand the objections. I'm happy that ARM followed through with
2019 May 24
2
[RFC][SVE] Supporting SIMD instruction sets with variable vector lengths
...i64 %index, mul (i64 %vscale64, i64 4) > %4 = icmp eq i64 %index.next, %n.vec > br i1 %4, label %middle.block, label %vector.body, !llvm.loop !5 > `` > > ========== > 7. Patches > ========== > > List of patches: > > 1. Extend VectorType: https://reviews.llvm.org/D32530 > 2. Vector element type Tablegen constraint: https://reviews.llvm.org/D47768 > 3. LLT support for scalable vectors: https://reviews.llvm.org/D47769 > 4. EVT strings and Type mapping: https://reviews.llvm.org/D47770 > 5. SVE Calling Convention: https://reviews.llvm.org/D47771 > 6. In...
2018 Jul 30
5
[RFC][SVE] Supporting SIMD instruction sets with variable vector lengths
...64 %index, mul (i64 %vscale64, i64 4) > %4 = icmp eq i64 %index.next, %n.vec > br i1 %4, label %middle.block, label %vector.body, !llvm.loop !5 > `` > > ========== > 8. Patches > ========== > > List of patches: > > 1. Extend VectorType: https://reviews.llvm.org/D32530 > 2. Vector element type Tablegen constraint: https://reviews.llvm.org/D47768 > 3. LLT support for scalable vectors: https://reviews.llvm.org/D47769 > 4. EVT strings and Type mapping: https://reviews.llvm.org/D47770 > 5. SVE Calling Convention: https://reviews.llvm.org/D47771 > 6. In...
2018 Jun 05
14
[RFC][SVE] Supporting SIMD instruction sets with variable vector lengths
...le used to increment loop index %index.next = add i64 %index, mul (i64 %vscale64, i64 4) %4 = icmp eq i64 %index.next, %n.vec br i1 %4, label %middle.block, label %vector.body, !llvm.loop !5 `` ========== 7. Patches ========== List of patches: 1. Extend VectorType: https://reviews.llvm.org/D32530 2. Vector element type Tablegen constraint: https://reviews.llvm.org/D47768 3. LLT support for scalable vectors: https://reviews.llvm.org/D47769 4. EVT strings and Type mapping: https://reviews.llvm.org/D47770 5. SVE Calling Convention: https://reviews.llvm.org/D47771 6. Intrinsic lowering cleanup:...
2019 May 24
2
[EXT] Re: [RFC][SVE] Supporting SIMD instruction sets with variable vector lengths
...le used to increment loop index %index.next = add i64 %index, mul (i64 %vscale64, i64 4) %4 = icmp eq i64 %index.next, %n.vec br i1 %4, label %middle.block, label %vector.body, !llvm.loop !5 `` ========== 7. Patches ========== List of patches: 1. Extend VectorType: https://reviews.llvm.org/D32530 2. Vector element type Tablegen constraint: https://reviews.llvm.org/D47768 3. LLT support for scalable vectors: https://reviews.llvm.org/D47769 4. EVT strings and Type mapping: https://reviews.llvm.org/D47770 5. SVE Calling Convention: https://reviews.llvm.org/D47771 6. Intrinsic lowering cleanup:...
2019 May 27
2
[EXT] Re: [RFC][SVE] Supporting SIMD instruction sets with variable vector lengths
...le used to increment loop index %index.next = add i64 %index, mul (i64 %vscale64, i64 4) %4 = icmp eq i64 %index.next, %n.vec br i1 %4, label %middle.block, label %vector.body, !llvm.loop !5 `` ========== 7. Patches ========== List of patches: 1. Extend VectorType: https://reviews.llvm.org/D32530 2. Vector element type Tablegen constraint: https://reviews.llvm.org/D47768 3. LLT support for scalable vectors: https://reviews.llvm.org/D47769 4. EVT strings and Type mapping: https://reviews.llvm.org/D47770 5. SVE Calling Convention: https://reviews.llvm.org/D47771 6. Intrinsic lowering cleanup:...
2018 Jul 30
7
[RFC][SVE] Supporting SIMD instruction sets with variable vector lengths
...>  br i1 %4, label %middle.block, label %vector.body, !llvm.loop !5 > > `` > > > > ========== > > 8. Patches > > ========== > > > > List of patches: > > > > 1. Extend VectorType: https://reviews.llvm.org/D32530 > > 2. Vector element type Tablegen constraint: > https://reviews.llvm.org/D47768 > > 3. LLT support for scalable vectors: https://reviews.llvm.org/D47769 > > 4. EVT strings and Type mapping: https://reviews.llvm.org/D47770 > > 5. SVE Calling Conventio...
2018 Jul 02
3
[RFC][SVE] Supporting SIMD instruction sets with variable vector lengths
...4 %index, mul (i64 %vscale64, i64 4) > %4 = icmp eq i64 %index.next, %n.vec > br i1 %4, label %middle.block, label %vector.body, !llvm.loop !5 > `` > > ========== > 8. Patches > ========== > > List of patches: > > 1. Extend VectorType: https://reviews.llvm.org/D32530 > 2. Vector element type Tablegen constraint: https://reviews.llvm.org/D47768 > 3. LLT support for scalable vectors: https://reviews.llvm.org/D47769 > 4. EVT strings and Type mapping: https://reviews.llvm.org/D47770 > 5. SVE Calling Convention: https://reviews.llvm.org/D47771 > 6. In...