Displaying 20 results from an estimated 51 matches for "d14".
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14
2012 Jun 09
0
bad mmio size, MMIO emulation failed, and other issues
...5 -> 0
(XEN) irq.c:270: Dom14 PCI link 1 changed 10 -> 0
(XEN) irq.c:270: Dom14 PCI link 2 changed 11 -> 0
(XEN) irq.c:270: Dom14 PCI link 3 changed 5 -> 0
(XEN) irq.c:2234: dom14: pirq 51 or emuirq 23 already mapped
(XEN) vmsi.c:108:d32767 Unsupported delivery mode 3
(XEN) emulate.c:88:d14 bad mmio size 16
(XEN) io.c:199:d14 MMIO emulation failed @ 0033:7fa98cc628b4: 66 0f 7f
0f 0f 28 56 10 0f 29
(XEN) stdvga.c:147:d14 entering stdvga and caching modes
(XEN) stdvga.c:151:d14 leaving stdvga
(XEN) emulate.c:88:d14 bad mmio size 16
(XEN) io.c:199:d14 MMIO emulation failed @ 0033:7f28312...
2010 Jul 05
2
nested for loops
...t results with memory allocation problems.
Thanks for your time and consideration.
for(d1 in 0:n){
for(d2 in 0:n){
for(d3 in 0:n){
for(d4 in 0:n){
for(d5 in 0:n){
for(d6 in 0:n){
for(d7 in 0:n){
for(d8 in 0:n){
for(d9 in 0:n){
for(d10 in 0:n){
for(d11 in 0:n){
for(d12 in 0:n){
for(d13 in 0:n){
for(d14 in 0:n){
for(d15 in 0:n){
for(d16 in 0:n){
for(d17 in 0:n){
for(d18 in 0:n){
for(d19 in 0:n){
for(d20 in 0:n){
list=c(d1,d2,d3,d4,d5,d6,d7,d8,d9,d10,d11,d12,d13,d14,d15,d16,d17,d18,d19,d20)
}}}}}}}}}}}}}}}}}}}}
[[alternative HTML version deleted]]
2010 May 30
0
How to interpret a result based on wmtsa
...d3 d4 d5 d6
272462.52504 189076.44195 95736.37691 47830.40918 23593.41513
12409.42279
d7 d8 d9 d10 d11 d12
5977.28418 2887.81182 1408.06198 629.46550 368.87030 197.00823
d13 d14 d15
106.22607 29.75633 14.29115
$EDOF2
[1] NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA
$EDOF3
d1 d2 d3 d4 d5 d6
2.079385e+05 1.039658e+05 5.197938e+04 2.598619e+04 1.298959e+04
6.491297e+03
d7 d8...
2020 Mar 31
2
[ARM] Register pressure with -mthumb forces register reload before each call
...CALLSTACKDOWN 0, 0, 14, $noreg, implicit-def dead $sp, implicit $sp
80B %3:tgpr = tLDRpci %const.0, 14, $noreg :: (load 4 from constant-pool)
96B $r0 = COPY %0:tgpr
112B $r1 = COPY %1:tgpr
128B $r2 = COPY %2:tgpr
144B tBLXr 14, $noreg, %3:tgpr, <regmask $lr $d8 $d9 $d10 $d11 $d12 $d13 $d14 $d15 $q4 $q5 $q6 $q7 $r4 $r5 $r6 $r7 $r8 $r9 $r10 $r11 $s16 $s17 $s18 $s19 $s20 $s21 $s22 $s23 $s24 $s25 $s26 $s27 and 35 more...>, implicit-def dead $lr, implicit $sp, implicit $r0, implicit $r1, implicit $r2, implicit-def $sp
160B ADJCALLSTACKUP 0, 0, 14, $noreg, implicit-def dead $sp, impli...
2020 Apr 07
2
[ARM] Register pressure with -mthumb forces register reload before each call
If I'm understanding what's going on in this test correctly, what's happening is:
* ARMTargetLowering::LowerCall prefers indirect calls when a function is called at least 3 times in minsize
* In thumb 1 (without -fno-omit-frame-pointer) we have effectively only 3 callee-saved registers (r4-r6)
* The function has three arguments, so those three plus the register we need to hold the
2020 Apr 15
4
[ARM] Register pressure with -mthumb forces register reload before each call
...CALLSTACKDOWN 0, 0, 14, $noreg, implicit-def dead $sp, implicit $sp
80B %3:tgpr = tLDRpci %const.0, 14, $noreg :: (load 4 from constant-pool)
96B $r0 = COPY %0:tgpr
112B $r1 = COPY %1:tgpr
128B $r2 = COPY %2:tgpr
144B tBLXr 14, $noreg, %3:tgpr, <regmask $lr $d8 $d9 $d10 $d11 $d12 $d13 $d14 $d15 $q4 $q5 $q6 $q7 $r4 $r5 $r6 $r7 $r8 $r9 $r10 $r11 $s16 $s17 $s18 $s19 $s20 $s21 $s22 $s23 $s24 $s25 $s26 $s27 and 35 more...>, implicit-def dead $lr, implicit $sp, implicit $r0, implicit $r1, implicit $r2, implicit-def $sp
160B ADJCALLSTACKUP 0, 0, 14, $noreg, implicit-def dead $sp, impli...
2015 Jul 30
0
[LLVMdev] [3.7.0] Two late issues with cross compilation to mips
...0 GPR32:%vreg253
4496B %vreg261<def> = FMUL_D32 %vreg247, %vreg248; AFGR64:%vreg261,%vreg247,%vreg248
4512B ADJCALLSTACKDOWN 16, %SP<imp-def>, %SP<imp-use>
4528B %D6<def> = COPY %vreg243; AFGR64:%vreg243
4544B JAL <ga:@sin>, <regmask %FP %RA %D10 %D11 %D12 %D13 %D14 %D15 %F20 %F21 %F22 %F23 %F24 %F25 %F26 %F27 %F28 %F29 %F30 %F31 %S0 %S1 %S2 %S3 %S4 %S5 %S6 %S7 >, %RA<imp-def,dead>, %D6<imp-use,kill>, %SP<imp-def>, %D0<imp-def>
4560B ADJCALLSTACKUP 16, 0, %SP<imp-def>, %SP<imp-use>
4576B %vreg262<def> = COPY %D0&l...
2012 Aug 21
2
[LLVMdev] Passing return values on the stack & storing arbitrary sized integers
> This isn't really my area of expertise, but I think you're messing up
> your RegisterClass definition. Look at how ARM defines DTriple.
DTriple is untyped :) , because we do not have any valut type which
defines 3xi64.
However, the paired register needs to have type.
Fabian, what are the definitions of ER and DR register classes?
--
With best regards, Anton Korobeynikov
Faculty
2012 Aug 21
0
[LLVMdev] Passing return values on the stack & storing arbitrary sized integers
...s of ER and DR register classes?
Hi Anton,
here are the definitions of these register classes:
// Data register class
def DR : RegisterClass<"TriCore", [i32], 32,
(add D0, D1, D2, D3, D4, D5, D6, D7,
D8, D9, D10, D11, D12, D13, D14, D15)>;
// Extended-size data register class
def ER : RegisterClass<"TriCore", [i64], 32,
(add E0, E2, E4, E6, E8, E10, E12, E14)> {
let SubRegClasses = [(DR sub_even, sub_odd)];
}
And the DX and EX registers are defined this way:
def D0 : TriCoreReg&...
2015 Jul 30
2
[LLVMdev] [3.7.0] Two late issues with cross compilation to mips
To reduce memory consumption clobbered registers are handled with RegisterMask machine operands which contain a bitset of all registers clobbered.
- Matthias
> On Jul 29, 2015, at 3:00 PM, Daniel Sanders <daniel.sanders at imgtec.com> wrote:
>
> I believe I've identified the problem with almabench but I haven't found the root cause in the compiler yet.
>
> The
2007 Aug 07
5
Extending RAIDZ.
...RAIDZ vdev, we have something like this:
Disk0 Disk1 Disk2 Disk3 NewDisk
<<P00 D00 D01 D02 U
P01 D03 D04 D05 U
P02 D06>> <<P03 D07>> U
<<P04 D08>> <<P05 D09 U
P06 D10 D11 D12>> U
<<P07 D13 D14 D15>> U
Then we start moving data, but we need to beging from the start:
Disk0 Disk1 Disk2 Disk3 NewDisk
<<N00 D00 D01 D02 D03
N01 D04 D05 D06>> <<P03
D07>> * U U U U
<<P04 D08>> <<P05 D09 U
P06 D10 D1...
2012 Aug 21
2
[LLVMdev] Passing return values on the stack & storing arbitrary sized integers
Fabian,
> here are the definitions of these register classes:
>
> // Data register class
> def DR : RegisterClass<"TriCore", [i32], 32,
> (add D0, D1, D2, D3, D4, D5, D6, D7,
> D8, D9, D10, D11, D12, D13, D14, D15)>;
>
> // Extended-size data register class
> def ER : RegisterClass<"TriCore", [i64], 32,
> (add E0, E2, E4, E6, E8, E10, E12, E14)> {
> let SubRegClasses = [(DR sub_even, sub_odd)];
> }
>
> And the DX and EX registers are de...
2012 Aug 22
2
[LLVMdev] Passing return values on the stack & storing arbitrary sized integers
...ons of these register classes:
>>>
>>> // Data register class
>>> def DR : RegisterClass<"TriCore", [i32], 32,
>>> (add D0, D1, D2, D3, D4, D5, D6, D7,
>>> D8, D9, D10, D11, D12, D13, D14, D15)>;
>>>
>>> // Extended-size data register class
>>> def ER : RegisterClass<"TriCore", [i64], 32,
>>> (add E0, E2, E4, E6, E8, E10, E12, E14)> {
>>> let SubRegClasses = [(DR sub_even, sub_odd)];
>>&...
2011 Jun 09
1
Error: missing values where TRUE/FALSE needed
...ts, lst$suffix2)
d6 = mytwo(prefix2, roots, suffix3)
d7 = mytwo(prefix, roots2, suffix)
d8 = mytwo(prefix, roots2, suffix2)
d9 = mytwo(prefix, roots2, suffix3)
d10 = mytwo(prefix2, roots2, suffix)
d11 = mytwo(prefix2, roots2, suffix2)
d12 = mytwo(prefix2, roots2, suffix3)
d13 = myone(prefix, roots)
d14 = myone(prefix2, roots)
d15 = myone(prefix, roots2)
d16 = myone(prefix2, roots2)
d17 = myone(roots, suffix)
d18 = myone(roots, suffix2)
d19 = myone(roots, suffix3)
d20 = myone(roots2, suffix)
d21 = myone(roots2, suffix2)
d22 = myone(roots2, suffix3)
d23 = myone(state, roots)
d24 = myone(city, roots...
2011 Jan 08
0
[LLVMdev] Unreachable executed with fast Regalloc and Sparc backend
...ifically but...
My guess is this is related to this entry in SparcInstrInfo.td:
let Uses = [O0, O1, O2, O3, O4, O5],
hasDelaySlot = 1, isCall = 1,
Defs = [O0, O1, O2, O3, O4, O5, O7, G1, G2, G3, G4, G5, G6, G7,
D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15] in {
def CALL : InstSP<(outs), (ins calltarget:$dst),
"call $dst", []> {
bits<30> disp;
let op = 1;
let Inst{29-0} = disp;
}
The Uses=[O0,O1,O2,O3,O4,O5] is causing this crash (and similar crashes in the PQBP a...
2012 Jun 25
0
[LLVMdev] RE : RE : Is llc broken for Cortex-A9 + neon ?
...# Machine code for function test_kernel: Post SSA
Frame Objects:
fi#-18: size=4, align=8, fixed, at location [SP+264]
...
Function Live Ins: %R2 in %vreg1, %R3 in %vreg2
BB#0: derived from LLVM BB %L.entry
Live Ins: %R2 %R3 %R4 %R5 %R6 %R7 %R8 %R9 %R10 %R11 %LR %D8 %D9 %D10 %D11 %D12 %D13 %D14 %D15
%SP<def> = STMDB_UPD %SP, pred:14, pred:%noreg, %R4<kill>, %R5<kill>, %R6<kill>, %R7<kill>, %R8<kill>, %R9<kill>, %R10<kill>, %R11<kill>, %LR<kill>; flags: FrameSetup
%SP<def> = VSTMDDB_UPD %SP, pred:14, pred:%noreg, %D8<ki...
2009 Sep 23
1
re peated measures
...wingless <- reshape(Wingless,
varying =
list(c("d0","d1","d2","d3","d4","d5","d6","d7","d8","d9","d10","d11","d12","d13","d14","d15","d16")),
v.names = c("fecundity"), timevar = "time",
direction = "long")
wingless.aov <- aov(fecundity ~ factor(time) * clip.cage * plant +
Error(factor(id)), data = wingless)...
2011 Jan 07
2
[LLVMdev] Unreachable executed with fast Regalloc and Sparc backend
Hello,
When I run LLC with option "-O0 -march=sparc" on following testcase,
fast register allocator crashes with "UNREACHABLE executed" error. LLC
generates code successfully with other standard register allocators
available.
$ cat call.ll
define void @test() nounwind {
entry:
%0 = tail call i32 (...)* @foo() nounwind
tail call void (...)* @bar() nounwind
ret void
}
2012 Jun 25
2
[LLVMdev] RE : Is llc broken for Cortex-A9 + neon ?
Hi Anton,
You're right it fails with a different message with llc 3.0.
Anyway thanks for your help.
Best Regards
Seb
> -----Original Message-----
> From: Anton Korobeynikov [mailto:anton at korobeynikov.info]
> Sent: Monday, June 25, 2012 3:39 PM
> To: Sebastien DELDON-GNB
> Cc: LLVMdev at cs.uiuc.edu; Rotem, Nadav
> Subject: Re: RE : [LLVMdev] Is llc broken for Cortex-A9
2012 Aug 22
0
[LLVMdev] Passing return values on the stack & storing arbitrary sized integers
...here are the definitions of these register classes:
>>
>> // Data register class
>> def DR : RegisterClass<"TriCore", [i32], 32,
>> (add D0, D1, D2, D3, D4, D5, D6, D7,
>> D8, D9, D10, D11, D12, D13, D14, D15)>;
>>
>> // Extended-size data register class
>> def ER : RegisterClass<"TriCore", [i64], 32,
>> (add E0, E2, E4, E6, E8, E10, E12, E14)> {
>> let SubRegClasses = [(DR sub_even, sub_odd)];
>> }
>>
>> An...