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...a “yes” then… -- Krzysztof Parzyszek kparzysz at quicinc.com<mailto:kparzysz at quicinc.com> AI tools development From: llvm-dev <llvm-dev-bounces at lists.llvm.org> On Behalf Of Krzysztof Parzyszek via llvm-dev Sent: Friday, September 27, 2019 10:05 AM To: Dangeti Tharun kumar <cs15mtech11002 at iith.ac.in>; llvm-dev at lists.llvm.org Subject: [EXT] Re: [llvm-dev] Question on target-features No. The way +feature works is that it causes the assignment Attribute=Value to happen, where Attribute and Value are strings defined in a td file. With -feature, this assignment does not happe...

On Mon, Jan 7, 2019 at 3:21 PM Dean Michael Berris <dean.berris at gmail.com> wrote: > On Mon, Jan 7, 2019 at 8:43 PM Dangeti Tharun kumar > <cs15mtech11002 at iith.ac.in> wrote: > > > > Hi Dean, > > > > I have tried with -instr-map-1 and -instr-map-2, it didn't work. > > > > Yeah, I'm looking through the code and it looks like we're always just > using the function id when we should be using the sy...

On Fri, Nov 2, 2018 at 3:31 PM Anton Korobeynikov <anton at korobeynikov.info> wrote: > > Yes, I am compiling for linux system. > > So the RA will not consider assigning a scratch register to a live range > crossing function call, though it may reduce spills? > Well, it has to spill the register – otherwise it could be clobbered by a > call. May be, I haven't

...it’s not immediate clear to me why we’re not distributing that. I think it’s s221() from TSVC. I will take a look later. Adam > > -Hal > > I humbly request the community to correct me, if am missing something in my analysis. > > -- > Thank you > D Tharun kumar > CS15MTECH11002 > 9948373970 > CSE-IITH > > _______________________________________________ > LLVM Developers mailing list > llvm-dev at lists.llvm.org <mailto:llvm-dev at lists.llvm.org> > http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev <http://lists.llvm.org/cgi-bin/mailman...

...the remark is "*loop not distributed: memory operations are safe for vectorization [-Rpass-analysis=loop-distribute]*". Can someone reason these results and this remark? I humbly request the community to correct me, if am missing something in my analysis. -- Thank you D Tharun kumar CS15MTECH11002 9948373970 CSE-IITH -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20161009/f5f8c81b/attachment.html>

Hi Dean, I have tried with -instr-map-1 and -instr-map-2, it didn't work. Is there a way to find the function name from the identifier? -DTharun On Mon, Jan 7, 2019 at 2:29 PM Dean Michael Berris <dean.berris at gmail.com> wrote: > Hi Dangeti, > > That's interesting -- can you try providing both `-instr-map-1=` and > `-instr-map-2=` even though they're the same

...ot com) Technical Lead of Vectorizer Development Intel Compiler and Languages ----------------------------------------------------------------------------- Message: 3 Date: Thu, 23 Jun 2016 10:45:28 -0700 From: Adam Nemet via llvm-dev <llvm-dev at lists.llvm.org> To: Dangeti Tharun kumar <cs15mtech11002 at iith.ac.in> Cc: llvm-dev at lists.llvm.org, Santanu Das <cs15mtech11018 at iith.ac.in> Subject: Re: [llvm-dev] Questions on LLVM vectorization diagnostics Message-ID: <B6F42D93-F676-4CB1-8413-A37A07490A55 at apple.com> Content-Type: text/plain; charset="utf-8" Hi Danget...

...77.2656890). References: - https://p4.org/ - P4 Paper DOI: http://dx.doi.org/10.1145/2656877.2656890 - Opensource P4 compiler https://github.com/p4lang/p4c - https://github.com/IITH-Compilers/p4lang *Thank you= Tharun, Venkat, Pankaj and Bhanu* -- D Tharun Kumar CS15MTECH11002 9948373970 CSE-IIT Hyderabad -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20180313/15effc99/attachment.html>

Hi, In "target-features" list in LLVM-IR, there are "+feature", "-feature". My question is, does "-feature" is equivalent to not specifying a feature at all? For example: *attributes #0 = { "target-cpu"="znver2" "target-features"="+avx -avx2" }* Wheather it is equalent to omitting the avx2 from list? *attributes #0

Dear LLVM Community, I am D Tharun Kumar, masters student at Indian Institute of Technology Hyderabad, working in a team to improve current vectorizer in LLVM. As an initial study, we are studying various benchmarks to analyze and compare vectorizing capabilities of LLVM, GCC and ICC. We found that vectorization remarks given by LLVM are vague and brief, comparatively GCC and ICC are giving

...; > The test case is from spec-17. > > The attached is the assembly file for the function MeanShiftImage from > spec17/538.imagick_r/src/magick/feature.c. > As I was saying, registers XMM10-15 are not used. > > > On Thu, Oct 25, 2018 at 2:16 PM Dangeti Tharun kumar < > cs15mtech11002 at iith.ac.in> wrote: > >> Hi, >> >> It can be reproduced with the following command: >> >> clang -S -I spec17/benchspec/CPU/538.imagick_r/src/ -O3 -mavx spec17/benchspec/CPU/538.imagick_r/src/magick/feature.c -DMAGICKCORE_HDRI_ENABLE >> >> I don'...

...swer. Thanks, Hideki Saito Intel Compilers and Languages -----Original Message----- From: ghoflehner at apple.com [mailto:ghoflehner at apple.com] Sent: Wednesday, August 24, 2016 5:38 PM To: Saito, Hideki <hideki.saito at intel.com> Cc: llvm-dev at lists.llvm.org; Dangeti Tharun kumar <cs15mtech11002 at iith.ac.in>; Santanu Das <cs15mtech11018 at iith.ac.in> Subject: Re: [llvm-dev] Questions on LLVM vectorization diagnostics Has there been a follow up? I’m very interested in specific examples underlying the key design decisions. Specifically I expect that you have examples that have a...

Hello, I have studied register allocation in theoretical aspects and exploring the same in the implementation level. I need a minimal testcase for register spilling to analyze spilling procedure in llvm. I tried with a testcase taking 20 variables but all the 20 variables are getting stored in the stack using %rbp. Maybe my live variable analysis is wrong. Please help me with a minimal testcase

Hi Hideki, Thanks for the interesting writeup! > On Aug 27, 2016, at 7:15 AM, Renato Golin via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > On 25 August 2016 at 05:46, Saito, Hideki via llvm-dev > <llvm-dev at lists.llvm.org> wrote: >> Now, I have one question. Suppose we'd like to split the vectorization decision as an Analysis pass and vectorization