search for: criticalantidepbreak

...64, <ga:@intrapred>[TF=3]; mem:LD8[GOT] %V0<def> = ADDu %ZERO, %T9<kill> ... JALR64 %S6_64<kill>, %A0_64<kill>, %A1<kill>, %A2<kill>, %A3<kill>, %T0<kill>, <regmask>, %SP<imp-def>, %V0<imp-def> ... $110 = void * CriticalAntiDepBreaker has replaced T9_64 with S6_64 to break an anti-dependence edge. This code is incorrect since the first operand of JALR64 has to be T9_64 in PIC mode. After further investigation, I found that the flag for T9_64 of CriticalAntiDepBreaker::KeepRegs that had been set in PrescanInstruction was reset...

In the course of implementing the instruction scheduler for the Intel Atom in LLVM, I have run across a problem with the critical anti-dependence breaker, whereby CriticalAntiDepBreak.cpp code changes some XMM0 references to be XMM9 references. This would be all well and good, were it not for the fact that the result of the expression needs to be in XMM0 because it is being returned as the function result in that register. The end of the original code sequence, prior to being p...

...sages. Then I added code in MipsPassConfig::addPreEmitPass() to prevent machine verifier from running post delay -slot-filler, and ran llc again. Again, there were no error messages. This is the list of passes run after post-RA scheduling. machine verifier is run twice after post RA scheduler (and CriticalAntiDepBreaker) is run. Post RA top-down list latency scheduler Verify generated machine code Analyze Machine Code For Garbage Collection Machine Block Frequency Analysis Branch Probability Basic Block Placement Verify generated machine code Mips Delay Slot Filler...

...in MipsPassConfig::addPreEmitPass() to prevent machine > verifier from running post delay -slot-filler, and ran llc again. Again, > there were no error messages. > > This is the list of passes run after post-RA scheduling. machine verifier > is run twice after post RA scheduler (and CriticalAntiDepBreaker) is run. > > Post RA top-down list latency scheduler > Verify generated machine code > Analyze Machine Code For Garbage Collection > Machine Block Frequency Analysis > Branch Probability Basic Block Placement > Verify generated machine code...

Hi Akira, > When I add -verify-machineinstrs, it complains that there are instructions > after terminator instructions. Yes, -verify-machineinstrs and -verify-coalescing are your friends here :) -- With best regards, Anton Korobeynikov Faculty of Mathematics and Mechanics, Saint Petersburg State University

Hi Anton, Thanks for the suggestions. I compiled the .ll file with llc with command line options -verify-dom-info, -verify-regalloc and -verify-loop-info. I didn't see any diagnostic messages. When I add -verify-machineinstrs, it complains that there are instructions after terminator instructions. It seems that these error messages are printed because the verifier does not understand that

Hi Akira, > I am running into a problem when I turn on post-RA scheduler with mode > "ANTIDEP_CRITICAL" for mips. > I'd appreciate if someone could explain what is going wrong here. All these passes are pretty sensitive to correct register liveness information. As a first step I'd check whether machine verifier reports no errors here. -- With best regards, Anton

...bLLVMCodeGen.a(AggressiveAntiDepBreaker.cpp.o) llvm::AggressiveAntiDepBreaker::PrescanInstruction(llvm::MachineInstr*, unsigned int, std::set<unsigned int, std::less<unsigned int>, std::allocator<unsigned int> >&)in libLLVMCodeGen.a(AggressiveAntiDepBreaker.cpp.o) llvm::CriticalAntiDepBreaker::ScanInstruction(llvm::MachineInstr*, unsigned int)in libLLVMCodeGen.a(CriticalAntiDepBreaker.cpp.o) llvm::CriticalAntiDepBreaker::PrescanInstruction(llvm::MachineInstr*) in libLLVMCodeGen.a(CriticalAntiDepBreaker.cpp.o) llvm::SimpleRegisterCoalescing::ReMaterializeTrivialDef(llvm::Liv...

Hello, Consider this code (this is all after register allocation): R0<def> = ... R0 // Set lower half (based on the previous value) R1<def> = ... // Set upper half ... = R0_R1 // Use the pair It is my understanding that the use of the whole pair will need to have some sort of a reaching def, i.e. the code will need at least those flags: R0<def> =

On Dec 8, 2009, at 3:31 PM, Jakob Stoklund Olesen wrote: > > On Dec 8, 2009, at 11:33 AM, Evan Cheng wrote: > >> This caused a massive slow down to post-ra scheduler (llc -O3 on x86, -O2 on ARM). I'm going to revert it for now until it has been addressed. > > Probably caused by this member: > > /// KillIndices - The index of the most recent kill (proceding

...ke[3]: Entering directory '/home/NIKHILREDDY/WORK/LLVM_OBJ/lib/Transforms/IPO' llvm[2]: Compiling CoreCLRGC.cpp for Release+Asserts build llvm[3]: Compiling ArgumentPromotion.cpp for Release+Asserts build llvm[3]: Compiling RuntimeDyldChecker.cpp for Release+Asserts build llvm[2]: Compiling CriticalAntiDepBreaker.cpp for Release+Asserts build llvm[3]: Compiling SpeculativeExecution.cpp for Release+Asserts build llvm[3]: Compiling RuntimeDyldELF.cpp for Release+Asserts build llvm[3]: Compiling StraightLineStrengthReduce.cpp for Release+Asserts build llvm[3]: Compiling BarrierNoopPass.cpp for Release+Assert...