search for: cpu1

I''m not sure if this is a problem with the iscsitarget or zfs. I''d greatly appreciate it if it gets moved to the proper list. Well I''m just about out of ideas on what might be wrong.. Quick history: I installed OS 2008.05 when it was SNV_86 to try out ZFS with VMWare. Found out that multilun''s were being treated as multipaths so waited till SNV_94 came out to

...e a bit of a misnomer. > +For example, switching to C code in deference to Herman Hollerith: > + > + int u, v, x, y, z; > + > + void cpu0(void) > + { > + r0 = smp_load_acquire(&x); > + WRITE_ONCE(u, 1); > + smp_store_release(&y, 1); > + } > + > + void cpu1(void) > + { > + r1 = smp_load_acquire(&y); > + r4 = READ_ONCE(v); > + r5 = READ_ONCE(u); > + smp_store_release(&z, 1); > + } > + > + void cpu2(void) > + { > + r2 = smp_load_acquire(&z); > + smp_store_release(&x, 1); > + } > + > + void...

...e a bit of a misnomer. > +For example, switching to C code in deference to Herman Hollerith: > + > + int u, v, x, y, z; > + > + void cpu0(void) > + { > + r0 = smp_load_acquire(&x); > + WRITE_ONCE(u, 1); > + smp_store_release(&y, 1); > + } > + > + void cpu1(void) > + { > + r1 = smp_load_acquire(&y); > + r4 = READ_ONCE(v); > + r5 = READ_ONCE(u); > + smp_store_release(&z, 1); > + } > + > + void cpu2(void) > + { > + r2 = smp_load_acquire(&z); > + smp_store_release(&x, 1); > + } > + > + void...

...k (as per the above) still sucks due to lock holder preemption, but at least the suckage doesn't queue. Because with queueing you not only have to worry about the lock holder getting preemption, but also the waiter(s). Take the situation of 3 (v)CPUs where cpu0 holds the lock but is preempted. cpu1 queues, cpu2 queues. Then cpu1 gets preempted, after which cpu0 gets back online. The simple test-and-set lock will now let cpu2 acquire. Your queue however will just sit there spinning, waiting for cpu1 to come back from holiday. I think you're way over engineering this. Just do the simple t...

...k (as per the above) still sucks due to lock holder preemption, but at least the suckage doesn't queue. Because with queueing you not only have to worry about the lock holder getting preemption, but also the waiter(s). Take the situation of 3 (v)CPUs where cpu0 holds the lock but is preempted. cpu1 queues, cpu2 queues. Then cpu1 gets preempted, after which cpu0 gets back online. The simple test-and-set lock will now let cpu2 acquire. Your queue however will just sit there spinning, waiting for cpu1 to come back from holiday. I think you're way over engineering this. Just do the simple t...

...following notifications: System Events =-=-=-=-=-=-= Nov 8 21:41:31 morpork acpid: received event "ac_adapter AC0 00000080 00000000" Nov 8 21:41:31 morpork acpid: completed event "ac_adapter AC0 00000080 00000000" Nov 8 21:41:31 morpork acpid: received event "processor CPU1 00000080 00000004" Nov 8 21:41:31 morpork acpid: completed event "processor CPU1 00000080 00000004" Nov 8 21:41:31 morpork acpid: received event "processor CPU1 00000081 00000000" Nov 8 21:41:31 morpork acpid: completed event "processor CPU1 00000081 00000000"...

...different physical cpus, or will that override the setting if there are too many interrupts and one of the cpus is overloaded. Example: i have 4 cpus and i have configured irqbalance= off, so there is no irqbalancing done by xen. Now if i have affintized all my physical interrutps to one cpu say cpu1 all the interrutps shpuld be handled by the cpu1 and so should all the softirqs generated. Now what happens if one of the other cpus is lightly loaded, will some of the softirqs be queued against the other cpus or will cpu1 handle all interrupts and softirqs. Looks to me like there are two levels...

Hi All! I have a some problem: On the my motherboard Intel DG45NB with Processor Box Intel Core 2 Duo E6300 , i see in the dmesg(log file): dmesg | grep CPU0 APIC error on CPU0: 00(60) or the sometime: dmesg | grep CPU1 APIC error on CPU1: 00(60) How can I fix this problem??? This Bug is my motherboard or the kernel??? The system good working is uptime... Without reboot... Other error in the log file - not found. My kernel 2.6.18-164.6.1.el5 My system CentOS 5.4...

...switch occurs right after vhost_dev_cleanup() frees > dev->iotlb, vhost_process_iotlb_msg() still sees the non-null value and it > keep executing without returning -EFAULT. Consequently, use-after-free > occures > > > Thread interleaving: > CPU0 (vhost_process_iotlb_msg) CPU1 (vhost_dev_cleanup) > (In the case of both VHOST_IOTLB_UPDATE and > VHOST_IOTLB_INVALIDATE) > ===== ===== > vhost_umem_clean(dev->iotlb); > if (!dev->iotlb) { > ret = -EFAULT; > break; > } > dev->iotlb = NULL; > > >...

...switch occurs right after vhost_dev_cleanup() frees > dev->iotlb, vhost_process_iotlb_msg() still sees the non-null value and it > keep executing without returning -EFAULT. Consequently, use-after-free > occures > > > Thread interleaving: > CPU0 (vhost_process_iotlb_msg) CPU1 (vhost_dev_cleanup) > (In the case of both VHOST_IOTLB_UPDATE and > VHOST_IOTLB_INVALIDATE) > ===== ===== > vhost_umem_clean(dev->iotlb); > if (!dev->iotlb) { > ret = -EFAULT; > break; > } > dev->iotlb = NULL; > > >...

On Thu, Jan 14, 2016 at 01:29:13PM -0800, Paul E. McKenney wrote: > So smp_mb() provides transitivity, as do pairs of smp_store_release() > and smp_read_acquire(), But they provide different grades of transitivity, which is where all the confusion lays. smp_mb() is strongly/globally transitive, all CPUs will agree on the order. Whereas the RCpc release+acquire is weakly so, only the two

On Thu, Jan 14, 2016 at 01:29:13PM -0800, Paul E. McKenney wrote: > So smp_mb() provides transitivity, as do pairs of smp_store_release() > and smp_read_acquire(), But they provide different grades of transitivity, which is where all the confusion lays. smp_mb() is strongly/globally transitive, all CPUs will agree on the order. Whereas the RCpc release+acquire is weakly so, only the two

...tlb_msg() still sees the non-null value > > > and it > > > keep executing without returning -EFAULT. Consequently, use-after-free > > > occures > > > > > > > > > Thread interleaving: > > > CPU0 (vhost_process_iotlb_msg)??????????????? CPU1 (vhost_dev_cleanup) > > > (In the case of both VHOST_IOTLB_UPDATE and > > > VHOST_IOTLB_INVALIDATE) > > > =====??????????????????????????? ===== > > > ??????????????????????????? vhost_umem_clean(dev->iotlb); > > > if (!dev->iotlb) { > > >...

...tlb_msg() still sees the non-null value > > > and it > > > keep executing without returning -EFAULT. Consequently, use-after-free > > > occures > > > > > > > > > Thread interleaving: > > > CPU0 (vhost_process_iotlb_msg)??????????????? CPU1 (vhost_dev_cleanup) > > > (In the case of both VHOST_IOTLB_UPDATE and > > > VHOST_IOTLB_INVALIDATE) > > > =====??????????????????????????? ===== > > > ??????????????????????????? vhost_umem_clean(dev->iotlb); > > > if (!dev->iotlb) { > > >...

...e CPUs on +the chain are guaranteed to agree on the combined order of the accesses. +For example, switching to C code in deference to Herman Hollerith: + + int u, v, x, y, z; + + void cpu0(void) + { + r0 = smp_load_acquire(&x); + WRITE_ONCE(u, 1); + smp_store_release(&y, 1); + } + + void cpu1(void) + { + r1 = smp_load_acquire(&y); + r4 = READ_ONCE(v); + r5 = READ_ONCE(u); + smp_store_release(&z, 1); + } + + void cpu2(void) + { + r2 = smp_load_acquire(&z); + smp_store_release(&x, 1); + } + + void cpu3(void) + { + WRITE_ONCE(v, 1); + smp_mb(); + r3 = READ_ONCE(u);...

...C code in deference to Herman Hollerith: > > + > > + int u, v, x, y, z; > > + > > + void cpu0(void) > > + { > > + r0 = smp_load_acquire(&x); > > + WRITE_ONCE(u, 1); > > + smp_store_release(&y, 1); > > + } > > + > > + void cpu1(void) > > + { > > + r1 = smp_load_acquire(&y); > > + r4 = READ_ONCE(v); > > + r5 = READ_ONCE(u); > > + smp_store_release(&z, 1); > > + } > > + > > + void cpu2(void) > > + { > > + r2 = smp_load_acquire(&z); > > + smp...

Hi, I am running a Xeon with hyperthreading support. Until last week's HTT modifications, according to ps(1) and top(1) both logicals CPUs were in use. (Processes in CPU0 and CPU1 state; "C" column showing "0" or "1".) This has changed with a recent -STABLE kernel which includes last week's changes to HTT (removing "options HTT"). I am only seeing processes on CPU0 and in "0" state in the "C" column. I am not s...

I see the following on one of my new servers: -ts10::sedwards:~$ cat /proc/interrupts CPU0 CPU1 CPU2 CPU3 0: 2979045 2988620 87780075 87779501 IO-APIC-edge timer 1: 1 3 2 3 IO-APIC-edge i8042 8: 0 0 0 1 IO-APIC-edge rtc 9: 0 0 0 0 IO-A...

...holder preemption, but at least the suckage doesn't queue. Because with > >queueing you not only have to worry about the lock holder getting > >preemption, but also the waiter(s). > > > >Take the situation of 3 (v)CPUs where cpu0 holds the lock but is > >preempted. cpu1 queues, cpu2 queues. Then cpu1 gets preempted, after > >which cpu0 gets back online. > > > >The simple test-and-set lock will now let cpu2 acquire. Your queue > >however will just sit there spinning, waiting for cpu1 to come back from > >holiday. > > > >I t...

...holder preemption, but at least the suckage doesn't queue. Because with > >queueing you not only have to worry about the lock holder getting > >preemption, but also the waiter(s). > > > >Take the situation of 3 (v)CPUs where cpu0 holds the lock but is > >preempted. cpu1 queues, cpu2 queues. Then cpu1 gets preempted, after > >which cpu0 gets back online. > > > >The simple test-and-set lock will now let cpu2 acquire. Your queue > >however will just sit there spinning, waiting for cpu1 to come back from > >holiday. > > > >I t...