I see the following on one of my new servers:
-ts10::sedwards:~$ cat /proc/interrupts
CPU0 CPU1 CPU2 CPU3
0: 2979045 2988620 87780075 87779501 IO-APIC-edge timer
1: 1 3 2 3 IO-APIC-edge i8042
8: 0 0 0 1 IO-APIC-edge rtc
9: 0 0 0 0 IO-APIC-level acpi
12: 13 13 15 17 IO-APIC-edge i8042
14: 909 53719 814685 763055 IO-APIC-edge ide0
169: 0 0 0 0 IO-APIC-level uhci_hcd,
uhci_hcd
177: 0 0 0 0 IO-APIC-level uhci_hcd
185: 0 0 0 0 IO-APIC-level uhci_hcd
193: 0 0 0 0 IO-APIC-level ehci_hcd
201: 665255896 107 123 122 IO-APIC-level eth0
217: 4298 2495 238514 233273 IO-APIC-level cciss0
225: 4611916 681023 84732445 89903138 IO-APIC-level wct4xxp
NMI: 0 0 0 0
LOC: 181534588 181534654 181534653 181534652
ERR: 0
MIS: 0
-ts10::sedwards:~$ ps -e | grep bal
2633 ? 00:00:00 irqbalance
Should I be concerned that cpu1 is servicing only 700,000 interrupts from
my te410p while cpu3 is servicing almost 90,000,000?
I thought this is what irqbalance was for...
Thanks in advance,
------------------------------------------------------------------------
Steve Edwards sedwards@sedwards.com Voice: +1-760-468-3867 PST
Newline Fax: +1-760-731-3000
Steve Edwards wrote:> Should I be concerned that cpu1 is servicing only 700,000 interrupts > from my te410p while cpu3 is servicing almost 90,000,000? > > I thought this is what irqbalance was for...Steve, It was my experience that irqbalance used smp affinity to bind the interrupts from each ethernet device to their own CPU. This led to uneven processor utilization on my Asterisk server, so after some research I turned off irqbalance. If you choose to do so, you'll want to confirm that your kernel has been configured to do IRQ balancing. For more details see: Asterisk & SMP: Is irqbalance Redundant on 2.6 Kernels? - Resolved <http://lists.digium.com/pipermail/asterisk-users/2006-March/146169.html> Matthew Roth InterMedia Marketing Solutions Software Engineer and Systems Developer
Steve Edwards <asterisk.org@sedwards.com> writes:> I see the following on one of my new servers: > > -ts10::sedwards:~$ cat /proc/interrupts > CPU0 CPU1 CPU2 CPU3 > 0: 2979045 2988620 87780075 87779501 IO-APIC-edge timer[...]> 225: 4611916 681023 84732445 89903138 IO-APIC-level wct4xxp > NMI: 0 0 0 0 > LOC: 181534588 181534654 181534653 181534652 > ERR: 0 > MIS: 0 > > -ts10::sedwards:~$ ps -e | grep bal > 2633 ? 00:00:00 irqbalance > > Should I be concerned that cpu1 is servicing only 700,000 interrupts > from my te410p while cpu3 is servicing almost 90,000,000? > > I thought this is what irqbalance was for...Actually, what you *really* want (for performance reasons) is to have one CPU handle *all* the interrupts and all the threads that talk to hardware for that card, if possible. Every time you move the IRQ to a different CPU you lose a bunch of cycles reloading data from main memory into the L2 and L1 cache, cycles that can't be used elsewhere. Binding that interrupt to one specific CPU -- and your NIC to a different CPU -- is generally a good idea. If you can keep the threads that handle those signals and the hardware on that same CPU you increase efficiency a bit more. Moving the IRQ has plenty of cost and isn't a great plan. :) Regards, Daniel -- Digital Infrastructure Solutions -- making IT simple, stable and secure Phone: 0401 155 707 email: contact@digital-infrastructure.com.au http://digital-infrastructure.com.au/