search for: cp15

...o Processor : ARM926EJ-Sid(wb) rev 3 (v5l) BogoMIPS : 95.83 (about 192 MHz) Features : swp half thumb fastmult edsp java CPU implementer : 0x41 CPU architecture: 5TEJ CPU variant : 0x0 CPU part : 0x926 CPU revision : 3 Cache type : write-back Cache clean : cp15 c7 ops Cache lockdown : format C Cache format : Harvard # gcc --version arm-linux-gcc (GCC) 3.3.2 (Debian) Configuration: --enable-fixed-point --enable-arm5e-asm Speex specs: Complexity 0, 8Kbps Encoding: ~95%, Decoding: ~44%, without Echo Cancellation / Pre-processor Does anyone know ho...

...is barely working on ARM at the moment. :) > I wonder if ARM32 BE is a real thing. I know that the processor is > bi-endian, but is there any system that uses ARM32 in big-endian mode? Yes... it is "a thing". :) ARM has two modes: BE32 and BE8 (mixed) and they can be enabled via CP15 registers. http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0290g/ch06s05s01.html cheers, --renato

...192 MHz) > > Features : swp half thumb fastmult edsp java > > CPU implementer : 0x41 > > CPU architecture: 5TEJ > > CPU variant : 0x0 > > CPU part : 0x926 > > CPU revision : 3 > > Cache type : write-back > > Cache clean : cp15 c7 ops > > Cache lockdown : format C > > Cache format : Harvard > > > > # gcc --version > > arm-linux-gcc (GCC) 3.3.2 (Debian) > > > > Configuration: --enable-fixed-point --enable-arm5e-asm > > > > Speex specs: Complexity 0, 8Kbps > >...

...5l) > BogoMIPS : 95.83 (about 192 MHz) > Features : swp half thumb fastmult edsp java > CPU implementer : 0x41 > CPU architecture: 5TEJ > CPU variant : 0x0 > CPU part : 0x926 > CPU revision : 3 > Cache type : write-back > Cache clean : cp15 c7 ops > Cache lockdown : format C > Cache format : Harvard > > # gcc --version > arm-linux-gcc (GCC) 3.3.2 (Debian) > > Configuration: --enable-fixed-point --enable-arm5e-asm > > Speex specs: Complexity 0, 8Kbps > Encoding: ~95%, Decoding: ~44%, without Echo C...

...x27# cat /proc/cpuinfo Processor ? ? ? : ARM926EJ-S rev 4 (v5l) BogoMIPS ? ? ? ?: 199.06 Features ? ? ? ?: swp half thumb fastmult edsp java CPU implementer : 0x41 CPU architecture: 5TEJ CPU variant ? ? : 0x0 CPU part ? ? ? ?: 0x926 CPU revision ? ?: 4 Cache type ? ? ?: write-back Cache clean ? ? : cp15 c7 ops Cache lockdown ?: format C Cache format ? ?: Harvard I size ? ? ? ? ?: 16384 I assoc ? ? ? ? : 4 I line length ? : 32 I sets ? ? ? ? ?: 128 D size ? ? ? ? ?: 16384 D assoc ? ? ? ? : 4 D line length ? : 32 D sets ? ? ? ? ?: 128 Hardware ? ? ? ?: Freescale i.MX27ADS Revision ? ? ? ?: 27021 Se...

Hi Ian, I try compile the bootwrapper for cubieboard2 like this: joshzhao@joshzhao-ThinkCentre-M58p:~/project/Xen/A20/boot-wrapper$ make cubieboard2_defconfig CROSS_COMPILE=arm-linux-gnueabihf- # # configuration written to .config # joshzhao@joshzhao-ThinkCentre-M58p:~/project/Xen/A20/boot-wrapper$ make CROSS_COMPILE=arm-linux-gnueabihf- make -C scripts/kconfig -f Makefile.bootwrapper

On Fri, Oct 28, 2016 at 2:56 PM, Richard Pennington via cfe-dev < cfe-dev at lists.llvm.org> wrote: > With all the talk about using lld on the list, I thought it would be > interesting to try using it in my clang based ELLCC cross compilation tool > chain. http://ellcc.org > > The change was simple, since I use configuration files to tell clang how > to compile, where to

...ofday.h index 36dc18553ed8..1b207cf07697 100644 --- a/arch/arm/include/asm/vdso/gettimeofday.h +++ b/arch/arm/include/asm/vdso/gettimeofday.h @@ -7,6 +7,7 @@ #ifndef __ASSEMBLY__ +#include <asm/barrier.h> #include <asm/errno.h> #include <asm/unistd.h> #include <asm/vdso/cp15.h> diff --git a/arch/arm64/include/asm/vdso/compat_gettimeofday.h b/arch/arm64/include/asm/vdso/compat_gettimeofday.h index b6907ae78e53..bcf7649999a4 100644 --- a/arch/arm64/include/asm/vdso/compat_gettimeofday.h +++ b/arch/arm64/include/asm/vdso/compat_gettimeofday.h @@ -7,6 +7,7 @@ #ifndef...

...4 > --- a/arch/arm/include/asm/vdso/gettimeofday.h > +++ b/arch/arm/include/asm/vdso/gettimeofday.h > @@ -7,6 +7,7 @@ > > #ifndef __ASSEMBLY__ > > +#include <asm/barrier.h> > #include <asm/errno.h> > #include <asm/unistd.h> > #include <asm/vdso/cp15.h> > diff --git a/arch/arm64/include/asm/vdso/compat_gettimeofday.h b/arch/arm64/include/asm/vdso/compat_gettimeofday.h > index b6907ae78e53..bcf7649999a4 100644 > --- a/arch/arm64/include/asm/vdso/compat_gettimeofday.h > +++ b/arch/arm64/include/asm/vdso/compat_gettimeofday.h > @...

Hello everyone, this is the fourth version of the patch series that introduces ARMv7 with virtualization extensions support in Xen. The series allows Xen and Dom0 to boot on a Cortex-A15 based Versatile Express simulator. See the following announce email for more informations about what we are trying to achieve, as well as the original git history: See

Hello everyone, this is the very first version of the patch series that introduces ARMv7 with virtualization extensions support in Xen. The series allows Xen and Dom0 to boot on a Cortex-A15 based Versatile Express simulator. See the following announce email for more informations about what we are trying to achieve, as well as the original git history: See

...00] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=6 [ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0 [ 0.000000] GIC: Using split EOI/Deactivate mode [ 0.000000] random: get_random_bytes called from start_kernel+0x2a8/0x434 with crng_init=0 [ 0.000000] arch_timer: cp15 timer(s) running at 31.25MHz (phys). [ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0xe6a171046, max_idle_ns: 881590405314 ns [ 0.000002] sched_clock: 56 bits at 31MHz, resolution 32ns, wraps every 4398046511088ns [ 0.008440] Console: colour dummy device 80x2...

...estricting CPUs from NR_CPUS=8 to nr_cpu_ids=6. [ 0.000000] Tasks RCU enabled. [ 0.000000] RCU: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=6 [ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0 [ 0.000000] GIC: Using split EOI/Deactivate mode [ 0.000000] arch_timer: cp15 timer(s) running at 31.25MHz (phys). [ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0xe6a171046, max_idle_ns: 881590405314 ns [ 0.000003] sched_clock: 56 bits at 31MHz, resolution 32ns, wraps every 4398046511088ns [ 0.000087] Console: colour dummy device 80x2...

Hi all, This is version three of the patches I previously posted here: v1: https://lore.kernel.org/lkml/20191108170120.22331-1-will at kernel.org/ v2: https://lore.kernel.org/r/20200630173734.14057-1-will at kernel.org Changes since v2 include: * Actually add the barrier in READ_ONCE() for Alpha! * Implement Alpha's smp_load_acquire() using __READ_ONCE(), rather than the other

Hello, This is the second version of this patch series. I only implement the VPF context switch support for arm32 and add dummy function to avoid compilation on arm64. I have switched the order of the patch because the old second one can be applied alone and the patch are cleaner :). For all the changes see each patch. Cheers, Julien Grall (2): xen/arm: don''t enable VFP on XEN

First off, Apologies for the massive patch series... This series boots a 32-bit dom0 kernel to a command prompt on an ARMv8 (AArch64) model. The kernel is the same one as I am currently using with the 32 bit hypervisor I haven''t yet tried starting a guest or anything super advanced like that ;-). Also there is not real support for 64-bit domains at all, although in one or two places I

Hi to all. I'm experimenting with running a https://www.zotac.com/us/product/graphics_card/geforce%C2%AE-gt-710-1gb-pcie-x-1 card on an Nvidia Jetson TX2 arm64 device. Possible? Linux kernel aarch64 5.6.10. Because Nvidia did not list drivers for this architecture, I'm experimenting with a nouveau driver. The Jetson TX2 has a default driver for the host1x framebuffer for output from the

This round implements all of the review comments from V2 and all patches are now acked. Unless there are any objections I intend to apply later this morning. Ian.

Thanks to Thierry for finding this - applying index e14643615698..00eeaaffeae5 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c @@ -2369,7 +2369,7 @@ nv13b_chipset = { .imem = gk20a_instmem_new, .ltc = gp100_ltc_new, .mc = gp10b_mc_new, - .mmu = gf100_mmu_new, + .mmu = gp10b_mmu_new,

...estricting CPUs from NR_CPUS=8 to nr_cpu_ids=6. [ 0.000000] Tasks RCU enabled. [ 0.000000] RCU: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=6 [ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0 [ 0.000000] GIC: Using split EOI/Deactivate mode [ 0.000000] arch_timer: cp15 timer(s) running at 31.25MHz (phys). [ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0xe6a171046, max_idle_ns: 881590405314 ns [ 0.000003] sched_clock: 56 bits at 31MHz, resolution 32ns, wraps every 4398046511088ns [ 0.000086] Console: colour dummy device 80x2...