Displaying 1 result from an estimated 1 matches for "core64".
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code64
2018 Jan 17
1
Opcodes with 32-bit pair vs 64-bit register
...1, "%r1">, DwarfRegNum<[1]>; def R2 : Core<2, "%r2">, DwarfRegNum<[2]>; def R3 : Core<3, "%r3">, DwarfRegNum<[3]>; def R0R1 : CorePair<0,"%r0",[R0,R1] >; def R2R3 : CorePair<2,"%r2",[R2,R3] >; def R0_64 : Core64<0, "%r0", [R0]>, DwarfRegNum<[0]>; def R1_64 : Core64<1, "%r1", [R1]>, DwarfRegNum<[1]>;
As I understand it, tablegen emits static tables with hard references to register classes and such. I fear that I'll need to duplicate all the opcodes that have...